From 5bc3569b0e5377dabb0ca311a1441e9170c63919 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 3 Sep 2021 10:26:38 -0500 Subject: [PATCH] Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR --- wally-pipelined/src/mmu/hptw.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv index 5962bd623..5ca5032e2 100644 --- a/wally-pipelined/src/mmu/hptw.sv +++ b/wally-pipelined/src/mmu/hptw.sv @@ -146,6 +146,7 @@ module hptw if (`XLEN == 32) begin assign InitialWalkerState = L1_ADR; assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0 + // *** Possible bug - should be L1_ADR? assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned); end else begin logic GigapageMisaligned, TerapageMisaligned;