diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 5962bd623..5ca5032e2 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -146,6 +146,7 @@ module hptw
 	  if (`XLEN == 32) begin
 		assign InitialWalkerState = L1_ADR;
 		assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
+	     // *** Possible bug - should be L1_ADR?
 		assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
 	  end else begin
 		logic  GigapageMisaligned, TerapageMisaligned;