From 00073155c53c58ac3a7a061d3e8315464d781343 Mon Sep 17 00:00:00 2001 From: Cedar Turek Date: Tue, 27 Dec 2022 21:34:27 -0800 Subject: [PATCH 1/2] Fixed cycles for multiple iterations. 2-copies radix 2 passing regression. --- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 743715b30..add717fe9 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -103,7 +103,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - cycles = MDUE ? (nE + 1) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + cycles = MDUE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */ From 6d933a88c758b8fd75637df61d9b07d83ab2b33e Mon Sep 17 00:00:00 2001 From: Cedar Turek Date: Tue, 27 Dec 2022 22:10:48 -0800 Subject: [PATCH 2/2] idiv passing radix 2, four copies --- pipelined/config/shared/wally-shared.vh | 2 +- pipelined/testbench/tests.vh | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index e6726eefe..cc24c42f6 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -110,7 +110,7 @@ // division constants `define RADIX 32'h2 -`define DIVCOPIES 32'h1 +`define DIVCOPIES 32'h4 `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : `NF+3) // `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input `define DIVN (`NF<`XLEN ? `XLEN : (`NF + 3)) // length of input diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 6ababb674..61e45d9e4 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -138,6 +138,7 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, + "rv32i_m/F/FSQRT-S-DYN-RDN-01", "rv32i_m/F/FADD-S-DYN-RDN-01", "rv32i_m/F/FADD-S-DYN-RMM-01", "rv32i_m/F/FADD-S-DYN-RNE-01",