Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

.gitignore

@@ -30,6 +30,7 @@ testsBP/*/*.a
 tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
 tests/riscof/riscof_work/
 tests/riscof/config32.ini
+tests/riscof/config32e.ini
 tests/riscof/config64.ini
 tests/linux-testgen/linux-testvectors/*
 !tests/linux-testgen/linux-testvectors/tvCopier.py

pipelined/config/rv64fp/wally-config.vh

@@ -32,7 +32,7 @@
 `define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
+`define XLEN 32
 
 // IEEE 754 compliance
 `define IEEE754 0

pipelined/config/shared/wally-shared.vh

@@ -102,8 +102,9 @@
 
 // division constants
 `define RADIX 32'h4
-`define DIVCOPIES 32'h1
+`define DIVCOPIES 32'h4
 `define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
+`define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
 `define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF) : 3)
 `define EXTRAINTBITS ((`NF<(`XLEN)) ? 0 : (`NF - `XLEN + 3))
 `define DIVRESLEN ((`NF>`XLEN) ? `NF+4 : `XLEN)
@@ -113,6 +114,7 @@
 `define FPDUR ((`DIVLEN+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4))
 `define DURLEN ($clog2(`FPDUR+1))
 `define QLEN (`FPDUR*`LOGR*`DIVCOPIES)
+`define DIVb (`FPDUR*`LOGR*`DIVCOPIES)-1
 
 
 `define USE_SRAM 0

pipelined/regression/Makefile

@@ -1,4 +1,4 @@
-all: archtests wallytests memfiles
+all: riscoftests memfiles
 	# *** Build old tests/imperas-riscv-tests for now;
 	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
 	# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
@@ -19,18 +19,13 @@ allclean: clean all
 
 clean:
 	make clean -C ../../tests/riscof
-	make clean -C ../../tests/wally-riscv-arch-test
+#   make clean -C ../../tests/wally-riscv-arch-test
 #	make allclean -C ../../tests/imperas-riscv-tests
 
-archtests:
+riscoftests: 
-	# Build riscv-arch-test 64 and 32-bit versions
+# 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
-	make -C ../../tests/riscof/ --jobs
+	make -C ../../tests/riscof/
-	make -C ../../tests/riscof/ XLEN=32 --jobs
+	make -C ../../tests/riscof/ XLEN=32
-
-wallytests:
-	# Build wally-riscv-arch-test
-	make -C ../../tests/wally-riscv-arch-test/ --jobs
-	make -C ../../tests/wally-riscv-arch-test/ XLEN=32  --jobs
 
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs

pipelined/regression/wave-fpu.do

@@ -32,8 +32,9 @@ add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/*
 add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/*
 # add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/otfc/otfc2/*
 # add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/qsel/qsel2/*
+add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/genblk1/qsel4/*
 add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/*
-# add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/expcalc/*
+add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/expcalc/*
 add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtfsm/*
 add wave -group {Testbench} -noupdate /testbenchfp/*
 add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*

pipelined/src/fpu/divshiftcalc.sv

@@ -1,8 +1,9 @@
 `include "wally-config.vh"
 
 module divshiftcalc(
-    input logic  [`QLEN-1-(`RADIX/4):0] DivQm,
+    input logic  [`DIVb-(`RADIX/4):0] DivQm,
     input logic  [`FMTBITS-1:0] Fmt,
+    input logic Sqrt,
     input logic [`DURLEN-1:0] DivEarlyTermShift,
     input logic [`NE+1:0] DivQe,
     output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
@@ -34,8 +35,8 @@ module divshiftcalc(
     assign NormShift = (`NE+2)'(`NF);
     // if the shift amount is negitive then dont shift (keep sticky bit)
     // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-    assign DivShiftAmt = (DivResDenorm ?  DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~DivDenormShift[`NE+1]}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
+    assign DivShiftAmt = (DivResDenorm ?  DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
 
-    assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`QLEN+(`RADIX/4)-`NF{1'b0}}};
+    assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
 
 endmodule

pipelined/src/fpu/divsqrt.sv

@@ -34,6 +34,7 @@ module divsqrt(
   input  logic clk, 
   input  logic reset, 
   input  logic [`FMTBITS-1:0] FmtE,
+  input  logic XsE,
   input  logic [`NF:0] XmE, YmE,
   input  logic [`NE-1:0] XeE, YeE,
   input  logic XInfE, YInfE, 
@@ -48,23 +49,22 @@ module divsqrt(
   output logic DivDone,
   output logic [`NE+1:0] QeM,
   output logic [`DURLEN-1:0] EarlyTermShiftM,
-  output logic [`QLEN-1-(`RADIX/4):0] QmM
+  output logic [`DIVb-(`RADIX/4):0] QmM
 //   output logic [`XLEN-1:0] RemM,
 );
 
-  logic [`DIVLEN+3:0]  NextWSN, NextWCN;
+  logic [`DIVb+3:0]  NextWSN, NextWCN;
-  logic [`DIVLEN+3:0]  WS, WC;
+  logic [`DIVb+3:0]  WS, WC;
-  logic [`DIVLEN+3:0] StickyWSA;
+  logic [`DIVb+3:0] StickyWSA;
-  logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
+  logic [`DIVb:0] X;
-  logic [`DIVLEN+3:0] X;
+  logic [`DIVN-2:0] Dpreproc;
-  logic [`DIVLEN+3:0] Dpreproc;
   logic [`DURLEN-1:0] Dur;
   logic NegSticky;
 
-  srtpreproc srtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, .XZeroCnt, .YZeroCnt);
+  srtpreproc srtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
 
-  srtfsm srtfsm(.reset, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE,
+  srtfsm srtfsm(.reset, .XsE, .SqrtE, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE,
                .StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM));
-  srt srt(.clk, .Sqrt(SqrtM), .X,.Dpreproc, .NegSticky, .XZeroCnt, .YZeroCnt, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
+  srt srt(.clk, .Sqrt(SqrtM), .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
-                .StickyWSA, .DivBusy, .Qm(QmM), .Rem());
+                .StickyWSA, .DivBusy, .Qm(QmM));
 endmodule

pipelined/src/fpu/fctrl.sv

@@ -178,14 +178,14 @@ module fctrl (
 
 // enables:
 //    X - all except int->fp, store, load, mv int->fp
-//    Y - all except cvt, mv, load, class
+//    Y - all except cvt, mv, load, class, sqrt
 //    Z - fma ops only
 //                  load/store                        mv int->fp                      cvt int->fp
     assign XEnE = ~(((FResSelE==2'b10)&~FWriteIntE)|((FResSelE==2'b11)&FRegWriteE)|((FResSelE==2'b01)&(PostProcSelE==2'b00)&OpCtrlE[2]));
 //                  load/class                                    mv               cvt
-    assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&(PostProcSelE==2'b00)));    
+    assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0]))));    
     assign ZEnE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&(~OpCtrlE[2]|OpCtrlE[1]);
-    assign YEnForwardE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&(PostProcSelE==2'b00)));    
+    assign YEnForwardE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0]))));    
     assign ZEnForwardE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&~OpCtrlE[2];
 
 //  Final Res Sel:

pipelined/src/fpu/flags.sv

@@ -126,11 +126,11 @@ module flags(
     //                  |                    |                    |                                      |                     and if the result is not exact
     //                  |                    |                    |                                      |                     |               and if the input isnt infinity or NaN
     //                  |                    |                    |                                      |                     |               |
-    assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&UfL)))&(R|S))&~(InfIn|NaNIn|DivByZero);
+    assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&UfL)))&(R|S))&~(InfIn|NaNIn|DivByZero|Invalid);
 
     // Set Inexact flag if the res is diffrent from what would be outputed given infinite precision
     //      - Don't set the underflow flag if an underflowed res isn't outputed
-    assign FpInexact = (S|Overflow|R)&~(InfIn|NaNIn|DivByZero);
+    assign FpInexact = (S|Overflow|R)&~(InfIn|NaNIn|DivByZero|Invalid);
 
     //                  if the res is too small to be represented and not 0
     //                  |                                     and if the res is not invalid (outside the integer bounds)
@@ -163,7 +163,7 @@ module flags(
 
     // if dividing by zero and not 0/0
     //  - don't set flag if an input is NaN or Inf(IEEE says has to be a finite numerator)
-    assign DivByZero = YZero&DivOp&~(XZero|NaNIn|InfIn);  
+    assign DivByZero = YZero&DivOp&~Sqrt&~(XZero|NaNIn|InfIn);  
 
     // Combine flags
     //      - to integer results do not set the underflow or overflow flags

pipelined/src/fpu/fpu.sv

@@ -125,7 +125,7 @@ module fpu (
    logic [`CVTLEN-1:0]     CvtLzcInE, CvtLzcInM;      // input to the Leading Zero Counter (priority encoder)
    
    //divide signals
-   logic [`QLEN-1-(`RADIX/4):0] QmM;
+   logic [`DIVb-(`RADIX/4):0] QmM;
    logic [`NE+1:0]      QeE, QeM; 
    logic                DivSE, DivSM;
    logic                DivDoneM;
@@ -260,7 +260,7 @@ module fpu (
    //    - fsqrt
    // *** add other opperations
    divsqrt divsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
-                  .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), 
+                  .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE,
                   .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
                   .EarlyTermShiftM, .QmM, .DivDone(DivDoneM));
    // compare

pipelined/src/fpu/otfc.sv

@@ -32,16 +32,16 @@
 
 module otfc2 (
   input  logic         qp, qz,
-  input  logic [`QLEN-1:0] Q, QM,
+  input  logic [`DIVb:0] Q, QM,
-  output logic [`QLEN-1:0] QNext, QMNext
+  output logic [`DIVb:0] QNext, QMNext
 );
   //  The on-the-fly converter transfers the quotient 
   //  bits to the quotient as they come.
   //  Use this otfc for division only.
-  logic [`QLEN-2:0] QR, QMR;
+  logic [`DIVb-1:0] QR, QMR;
 
-  assign QR  = Q[`QLEN-2:0];
+  assign QR  = Q[`DIVb-1:0];
-  assign QMR = QM[`QLEN-2:0];     // Shifted Q and QM
+  assign QMR = QM[`DIVb-1:0];     // Shifted Q and QM
 
   always_comb begin
     if (qp) begin
@@ -96,8 +96,8 @@ endmodule
 
 module otfc4 (
   input  logic [3:0]   q,
-  input  logic [`QLEN-1:0] Q, QM,
+  input  logic [`DIVb:0] Q, QM,
-  output logic [`QLEN-1:0] QNext, QMNext
+  output logic [`DIVb:0] QNext, QMNext
 );
 
   //  The on-the-fly converter transfers the quotient 
@@ -113,7 +113,7 @@ module otfc4 (
   //  QR and QMR are the shifted versions of Q and QM.
   //  They are treated as [N-1:r] size signals, and 
   //  discard the r most significant bits of Q and QM. 
-  logic [`QLEN-3:0] QR, QMR;
+  logic [`DIVb-2:0] QR, QMR;
 
   // shift Q (quotent) and QM (quotent-1)
 		// if 	q = 2  	    Q = {Q, 10} 	QM = {Q, 01}		
@@ -122,8 +122,8 @@ module otfc4 (
 		// else if 	q = -1	Q = {QM, 11} 	QM = {QM, 10}
 		// else if 	q = -2	Q = {QM, 10} 	QM = {QM, 01}
 
-  assign QR  = Q[`QLEN-3:0];
+  assign QR  = Q[`DIVb-2:0];
-  assign QMR = QM[`QLEN-3:0];     // Shifted Q and QM
+  assign QMR = QM[`DIVb-2:0];     // Shifted Q and QM
   always_comb begin
     if (q[3]) begin // +2
       QNext  = {QR,  2'b10};

pipelined/src/fpu/postprocess.sv

@@ -60,7 +60,7 @@ module postprocess (
     input logic                             DivS,
     input logic                             DivDone,
     input logic  [`NE+1:0]                  DivQe,
-    input logic  [`QLEN-1-(`RADIX/4):0]                DivQm,
+    input logic  [`DIVb-(`RADIX/4):0]                DivQm,
     // conversion signals
     input logic                             CvtCs,     // the result's sign
     input logic  [`NE:0]                    CvtCe,    // the calculated expoent
@@ -154,7 +154,7 @@ module postprocess (
                               .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
     fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe,
                           .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
-    divshiftcalc divshiftcalc(.Fmt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
+    divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
 
     always_comb
         case(PostProcSel)
@@ -199,7 +199,7 @@ module postprocess (
 
                           
     roundsign roundsign(.FmaPs, .FmaAs, .FmaInvA, .FmaOp, .DivOp, .CvtOp, .FmaNegSum, 
-                        .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
+                        .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
 
     round round(.OutFmt, .Frm, .S, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe,
                 .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt,  .CvtResUf,

pipelined/src/fpu/qsel.sv

@@ -89,17 +89,17 @@ module fgen2 (
 endmodule
 
 module qsel4 (
-	input logic [`DIVLEN+3:0] D,
+	input logic [`DIVN-2:0] D,
-	input logic [`DIVLEN+3:0] WS, WC,
+	input logic [`DIVb+3:0] WS, WC,
   input logic Sqrt,
 	output logic [3:0] q
 );
 	logic [6:0] Wmsbs;
 	logic [7:0] PreWmsbs;
 	logic [2:0] Dmsbs;
-	assign PreWmsbs = WC[`DIVLEN+3:`DIVLEN-4] + WS[`DIVLEN+3:`DIVLEN-4];
+	assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4];
 	assign Wmsbs = PreWmsbs[7:1];
-	assign Dmsbs = D[`DIVLEN-1:`DIVLEN-3];
+	assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}};
 	// D = 0001.xxx...
 	// Dmsbs = |   |
   // W =      xxxx.xxx...
@@ -177,8 +177,8 @@ module fgen4 (
   assign F2  = (~S << 2) & (C << 2);
   assign F1  = ~(S << 1) & C;
   assign F0  = '0;
-  assign FN1 = (SM << 1) | (C & ~(C << 2));
+  assign FN1 = (SM << 1) | (C & ~(C << 3));
-  assign FN2 = (SM << 2) | ((C << 2)&~(C <<4));
+  assign FN2 = (SM << 2) | ((C << 2)&~(C << 4));
 
   // Choose which adder input will be used
 

pipelined/src/fpu/roundsign.sv

@@ -34,6 +34,7 @@ module roundsign(
     input logic         Xs,
     input logic         Ys,
     input logic         FmaNegSum,
+    input logic         Sqrt,
     input logic         FmaOp,
     input logic         DivOp,
     input logic         CvtOp,
@@ -44,7 +45,7 @@ module roundsign(
 
     logic Qs;
 
-    assign Qs = Xs^Ys;
+    assign Qs = Xs^(Ys&~Sqrt);
 
     // Sign for rounding calulation
     assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp);

pipelined/src/fpu/srt.sv

@@ -37,40 +37,43 @@ module srt(
   input  logic [`NE-1:0] Xe, Ye,
   input  logic XZeroE, YZeroE, 
   input  logic Sqrt,
-  input  logic [`DIVLEN+3:0] X,
+  input  logic [`DIVb:0] X,
-  input  logic [`DIVLEN+3:0] Dpreproc,
+  input  logic [`DIVN-2:0] Dpreproc,
-  input  logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt,
   input  logic NegSticky,
-  output logic [`QLEN-1-(`RADIX/4):0] Qm,
+  output logic [`DIVb-(`RADIX/4):0] Qm,
-  output logic [`DIVLEN+3:0]  NextWSN, NextWCN,
+  output logic [`DIVb+3:0]  NextWSN, NextWCN,
-  output logic [`DIVLEN+3:0]  StickyWSA,
+  output logic [`DIVb+3:0]  StickyWSA,
-  output logic [`DIVLEN+3:0]  FirstWS, FirstWC,
+  output logic [`DIVb+3:0]  FirstWS, FirstWC
-  output logic [`XLEN-1:0] Rem
 );
 
-
+//QLEN = 1.(number of bits created for division)
+// N is NF+1 or XLEN
+// WC/WS is dependent on D so 4.N-1 ie N+3 bits or N+2:0 + one more bit in fraction for possible sqrt right shift
+// D is 1.N-1, but the msb is always 1 so 0.N-1 or N-1 bits or N-1:0
+// Dsel should match WC/WS so 4.N-1 ie N+3 bits or N+2:0
+// Q/QM/S/SM should be 1.b so b+1 bits or b:0
+// C needs to be the lenght of the final fraction 0.b so b or b-1:0
  /* verilator lint_off UNOPTFLAT */
-  logic [`DIVLEN+3:0]  WSA[`DIVCOPIES-1:0];
+  logic [`DIVb+3:0]  WSA[`DIVCOPIES-1:0]; // Q4.b
-  logic [`DIVLEN+3:0]  WCA[`DIVCOPIES-1:0];
+  logic [`DIVb+3:0]  WCA[`DIVCOPIES-1:0]; // Q4.b
-  logic [`DIVLEN+3:0]  WS[`DIVCOPIES-1:0];
+  logic [`DIVb+3:0]  WS[`DIVCOPIES-1:0]; // Q4.b
-  logic [`DIVLEN+3:0]  WC[`DIVCOPIES-1:0];
+  logic [`DIVb+3:0]  WC[`DIVCOPIES-1:0]; // Q4.b
-  logic [`QLEN-1:0] Q[`DIVCOPIES-1:0];
+  logic [`DIVb:0] Q[`DIVCOPIES-1:0]; // U1.b
-  logic [`QLEN-1:0] QM[`DIVCOPIES-1:0];
+  logic [`DIVb:0] QM[`DIVCOPIES-1:0];// 1.b
-  logic [`QLEN-1:0] QNext[`DIVCOPIES-1:0];
+  logic [`DIVb:0] QNext[`DIVCOPIES-1:0];// U1.b
-  logic [`QLEN-1:0] QMNext[`DIVCOPIES-1:0];
+  logic [`DIVb:0] QMNext[`DIVCOPIES-1:0];// U1.b
-  logic [`DIVLEN+3:0] S[`DIVCOPIES-1:0]; //***change to QLEN???
+  logic [`DIVb:0] S[`DIVCOPIES-1:0];// U1.b
-  logic [`DIVLEN+3:0] SM[`DIVCOPIES-1:0];
+  logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b
-  logic [`DIVLEN+3:0] SNext[`DIVCOPIES-1:0];
+  logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b
-  logic [`DIVLEN+3:0] SMNext[`DIVCOPIES-1:0];
+  logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b
-  logic [`DIVLEN+3:0] C[`DIVCOPIES-1:0];
+  logic [`DIVb-1:0] C[`DIVCOPIES-1:0]; // 0.b
  /* verilator lint_on UNOPTFLAT */
-  logic [`DIVLEN+3:0]  WSN, WCN;
+  logic [`DIVb+3:0]  WSN, WCN; // Q4.N-1
-  logic [`DIVLEN+3:0]  D, DBar, D2, DBar2;
+  logic [`DIVN-2:0]  D; // U0.N-1
-  logic [$clog2(`XLEN+1)-1:0] intExp;
+  logic [`DIVb+3:0]  DBar, D2, DBar2; // Q4.N-1
-  logic           intSign;
+  logic [`DIVb:0] QMMux;
-  logic [`QLEN-1:0] QMMux;
+  logic [`DIVb-1:0] CMux;
-  logic [`DIVLEN+3:0] CMux;
+  logic [`DIVb:0] SMux;
-  logic [`DIVLEN+3:0] SMux;
 
   // Top Muxes and Registers
   // When start is asserted, the inputs are loaded into the divider.
@@ -81,27 +84,28 @@ module srt(
   //  - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection)
   //  - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized
   if (`RADIX == 2) begin : nextw
-    assign NextWSN = {WSA[`DIVCOPIES-1][`DIVLEN+2:0], 1'b0};
+    assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
-    assign NextWCN = {WCA[`DIVCOPIES-1][`DIVLEN+2:0], 1'b0};
+    assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0};
   end else begin
-    assign NextWSN = {WSA[`DIVCOPIES-1][`DIVLEN+1:0], 2'b0};
+    assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
-    assign NextWCN = {WCA[`DIVCOPIES-1][`DIVLEN+1:0], 2'b0};
+    assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0};
   end
 
-  mux2   #(`DIVLEN+4) wsmux(NextWSN, X, DivStart, WSN);
+  mux2   #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN);
-  flopen   #(`DIVLEN+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
+  flopen   #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]);
-  mux2   #(`DIVLEN+4) wcmux(NextWCN, {`DIVLEN+4{1'b0}}, DivStart, WCN);
+  mux2   #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN);
-  flopen   #(`DIVLEN+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
+  flopen   #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]);
-  flopen #(`DIVLEN+4) dflop(clk, DivStart, Dpreproc, D);
+  flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D);
-  mux2 #(`DIVLEN+4) Cmux({2'b11, C[`DIVCOPIES-1][`DIVLEN+3:2]}, {5'b11111, Sqrt, {(`DIVLEN-2){1'b0}}}, DivStart, CMux);
+  mux2 #(`DIVb) Cmux({2'b11, C[`DIVCOPIES-1][`DIVb-1:2]}, {Sqrt, {(`DIVb-1){1'b0}}}, DivStart, CMux);
-  flop #(`DIVLEN+4) cflop(clk, CMux, C[0]);
+  flop #(`DIVb) cflop(clk, CMux, C[0]);
 
   // Divisor Selections
-  // - choose the negitive version of what's being selected
+  //  - choose the negitive version of what's being selected
-  assign DBar = ~D;
+  //  - D is only the fraction
+  assign DBar = {3'b111, 1'b0, ~D, {`DIVb-`DIVN+1{1'b1}}};
   if(`RADIX == 4) begin : d2
-    assign DBar2 = {~D[`DIVLEN+2:0], 1'b1};
+    assign DBar2 = {2'b11, 1'b0, ~D, {`DIVb+2-`DIVN{1'b1}}};
-    assign D2 = {D[`DIVLEN+2:0], 1'b0};
+    assign D2 = {2'b0, 1'b1, D, {`DIVb+2-`DIVN{1'b0}}};
   end
 
   genvar i;
@@ -112,12 +116,13 @@ module srt(
       .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i]));
       if(i<(`DIVCOPIES-1)) begin 
         if (`RADIX==2)begin 
-          assign WS[i+1] = {WSA[i][`DIVLEN+1:0], 1'b0};
+          assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0};
-          assign WC[i+1] = {WCA[i][`DIVLEN+1:0], 1'b0};
+          assign WC[i+1] = {WCA[i][`DIVb+2:0], 1'b0};
+          assign  C[i+1] = {1'b1, C[i][`DIVb-1:1]};
         end else begin
-          assign WS[i+1] = {WSA[i][`DIVLEN+1:0], 2'b0};
+          assign WS[i+1] = {WSA[i][`DIVb+1:0], 2'b0};
-          assign WC[i+1] = {WCA[i][`DIVLEN+1:0], 2'b0};
+          assign WC[i+1] = {WCA[i][`DIVb+1:0], 2'b0};
-          assign  C[i+1] = {2'b11, C[i][`DIVLEN+3:2]};
+          assign  C[i+1] = {2'b11, C[i][`DIVb-1:2]};
         end
         assign Q[i+1] = QNext[i];
         assign QM[i+1] = QMNext[i];
@@ -128,30 +133,30 @@ module srt(
   endgenerate
 
   // if starting a new divison set Q to 0 and QM to -1
-  mux2 #(`QLEN) QMmux(QMNext[`DIVCOPIES-1], {`QLEN{1'b1}}, DivStart, QMMux);
+  mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
-  flopenr #(`QLEN) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
+  flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
-  flopen #(`QLEN) QMreg(clk, DivBusy, QMMux, QM[0]);
+  flopen #(`DIVb+1) QMreg(clk, DivBusy, QMMux, QM[0]);
-
-  flopr #(`DIVLEN+4) SMreg(clk, DivStart, SMNext[`DIVCOPIES-1], SM[0]);
-  mux2 #(`DIVLEN+4) Smux(SNext[`DIVCOPIES-1], {3'b000, Sqrt, {(`DIVLEN){1'b0}}}, DivStart, SMux);
-  flop #(`DIVLEN+4) Sreg(clk, SMux, S[0]);
 
+  flopr #(`DIVb+1) SMreg(clk, DivStart, SMNext[`DIVCOPIES-1], SM[0]);
+  mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {Sqrt, {(`DIVb){1'b0}}}, DivStart, SMux);
+  flop #(`DIVb+1) Sreg(clk, SMux, S[0]);
+ // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
   always_comb
-    if(Sqrt)
+    if(Sqrt) // sqrt ouputs in the range (1, .5]
-      if(NegSticky) Qm = SM[0][`QLEN-1-(`RADIX/4):0];
+      if(NegSticky) Qm = {SM[0][`DIVb-1-(`RADIX/4):0], 1'b0};
-      else          Qm = S[0][`QLEN-1-(`RADIX/4):0];
+      else          Qm = {S[0][`DIVb-1-(`RADIX/4):0], 1'b0};
     else  
-      if(NegSticky) Qm = QM[0][`QLEN-1-(`RADIX/4):0];
+      if(NegSticky) Qm = QM[0][`DIVb-(`RADIX/4):0];
-      else          Qm = Q[0][`QLEN-1-(`RADIX/4):0];
+      else          Qm = Q[0][`DIVb-(`RADIX/4):0];
 
   assign FirstWS = WS[0];
   assign FirstWC = WC[0];
 
   if(`RADIX==2)
     if (`DIVCOPIES == 1)
-      assign StickyWSA = {WSA[0][`DIVLEN+2:0], 1'b0};
+      assign StickyWSA = {WSA[0][`DIVb+2:0], 1'b0};
     else
-      assign StickyWSA = {WSA[1][`DIVLEN+2:0], 1'b0};
+      assign StickyWSA = {WSA[1][`DIVb+2:0], 1'b0};
 
 
 endmodule
@@ -162,24 +167,24 @@ endmodule
 
  /* verilator lint_off UNOPTFLAT */
 module divinteration (
-  input logic [`DIVLEN+3:0] D,
+  input logic [`DIVN-2:0] D,
-  input logic [`DIVLEN+3:0]  DBar, D2, DBar2,
+  input logic [`DIVb+3:0]  DBar, D2, DBar2,
-  input logic [`QLEN-1:0] Q, QM,
+  input logic [`DIVb:0] Q, QM,
-  input logic [`DIVLEN+3:0] S, SM,
+  input logic [`DIVb:0] S, SM,
-  input logic [`DIVLEN+3:0]  WS, WC,
+  input logic [`DIVb+3:0]  WS, WC,
-  input logic [`DIVLEN+3:0] C,
+  input logic [`DIVb-1:0] C,
   input logic Sqrt,
-  output logic [`QLEN-1:0] QNext, QMNext, 
+  output logic [`DIVb:0] QNext, QMNext, 
-  output logic [`DIVLEN+3:0] SNext, SMNext, 
+  output logic [`DIVb:0] SNext, SMNext, 
-  output logic [`DIVLEN+3:0]  WSA, WCA
+  output logic [`DIVb+3:0]  WSA, WCA
 );
  /* verilator lint_on UNOPTFLAT */
 
-  logic [`DIVLEN+3:0]  Dsel;
+  logic [`DIVb+3:0]  Dsel;
   logic [3:0]     q;
-  logic qp, qz;//, qn;
+  logic qp, qz;
-  logic [`DIVLEN+3:0] F;
+  logic [`DIVb+3:0] F;
-  logic [`DIVLEN+3:0] AddIn;
+  logic [`DIVb+3:0] AddIn;
 
   // Qmient Selection logic
   // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
@@ -190,21 +195,21 @@ module divinteration (
 	// 0010 = -1
 	// 0001 = -2
   if(`RADIX == 2) begin : qsel
-    qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], qp, qz);//, qn);
+    qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz);
   end else begin
     qsel4 qsel4(.D, .WS, .WC, .Sqrt, .q);
-    fgen4 fgen4(.s(q), .C, .S, .SM, .F);
+    // fgen4 fgen4(.s(q), .C, .S, .SM, .F);
   end
 
   if(`RADIX == 2) begin : dsel
-    assign Dsel = {`DIVLEN+4{~qz}}&(qp ? DBar : D);
+    assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}});
   end else begin
     always_comb
       case (q)
         4'b1000: Dsel = DBar2;
         4'b0100: Dsel = DBar;
         4'b0000: Dsel = '0;
-        4'b0010: Dsel = D;
+        4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}};
         4'b0001: Dsel = D2;
         default: Dsel = 'x;
       endcase
@@ -213,16 +218,16 @@ module divinteration (
   //  WSA, WCA = WS + WC - qD
   assign AddIn = Sqrt ? F : Dsel;
   if (`RADIX == 2) begin : csa
-    csa #(`DIVLEN+4) csa(WS, WC, AddIn, qp, WSA, WCA);
+    csa #(`DIVb+4) csa(WS, WC, AddIn, qp, WSA, WCA);
   end else begin
-    csa #(`DIVLEN+4) csa(WS, WC, AddIn, |q[3:2], WSA, WCA);
+    csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~Sqrt, WSA, WCA);
   end
 
   if (`RADIX == 2) begin : otfc
     otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext);
   end else begin
     otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
-    sotfc4 sotfc4(.s(q), .Sqrt, .C, .S, .SM, .SNext, .SMNext);
+    // sotfc4 sotfc4(.s(q), .Sqrt, .C, .S, .SM, .SNext, .SMNext);
   end
 
 endmodule

pipelined/src/fpu/srtfsm.sv

@@ -33,14 +33,16 @@
 module srtfsm(
   input  logic clk, 
   input  logic reset, 
-  input logic [`DIVLEN+3:0] NextWSN, NextWCN, WS, WC,
+  input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC,
   input  logic XInfE, YInfE, 
   input  logic XZeroE, YZeroE, 
   input  logic XNaNE, YNaNE, 
   input  logic DivStart, 
+  input  logic XsE,
+  input  logic SqrtE,
   input  logic StallE,
   input  logic StallM,
-  input  logic [`DIVLEN+3:0] StickyWSA,
+  input  logic [`DIVb+3:0] StickyWSA,
   input  logic [`DURLEN-1:0] Dur,
   output logic [`DURLEN-1:0] EarlyTermShiftE,
   output logic DivSE,
@@ -55,11 +57,11 @@ module srtfsm(
   logic [`DURLEN-1:0] step;
   logic WZero;
   //logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
-  logic [`DIVLEN+3:0] W;
+  logic [`DIVb+3:0] W;
 
   //flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
   assign DivBusy = (state == BUSY);
-  assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVLEN+2:0]|NextWCN[`DIVLEN+2:0], 1'b0});
+  assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
   // calculate sticky bit
   //    - there is a chance that a value is subtracted infinitly, resulting in an exact QM result
   //      this is only a problem on radix 2 (and pssibly maximally redundant 4) since minimally redundant
@@ -70,7 +72,7 @@ module srtfsm(
     assign DivSE = |W;
   assign DivDone = (state == DONE);
   assign W = WC+WS;
-  assign NegSticky = W[`DIVLEN+3]; //*** is there a better way to do this???
+  assign NegSticky = W[`DIVb+3];
   assign EarlyTermShiftE = step;
 
   always_ff @(posedge clk) begin
@@ -78,7 +80,7 @@ module srtfsm(
           state <= #1 IDLE; 
       end else if (DivStart&~StallE) begin 
           step <= Dur;
-          if (XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE) state <= #1 DONE;
+          if (XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE;
           else         state <= #1 BUSY;
       end else if (state == BUSY) begin
           if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin

pipelined/src/fpu/srtpreproc.sv

@@ -39,16 +39,16 @@ module srtpreproc (
   input  logic Sqrt,
   input logic XZero,
   output logic  [`NE+1:0] QeM,
-  output logic [`DIVLEN+3:0] X,
+  output logic [`DIVb:0] X,
-  output logic [`DIVLEN+3:0] Dpreproc,
+  output logic [`DIVN-2:0] Dpreproc,
-  output logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt,
   output logic [`DURLEN-1:0] Dur
 );
   // logic  [`XLEN-1:0] PosA, PosB;
   // logic  [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
   logic  [`NF-1:0] PreprocA, PreprocX;
   logic  [`NF-1:0] PreprocB, PreprocY;
-  logic  [`NF+3:0] SqrtX;
+  logic  [`NF+1:0] SqrtX;
+  logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
   logic [`NE+1:0] Qe;
 
   // assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
@@ -70,9 +70,9 @@ module srtpreproc (
   assign PreprocY = Ym[`NF-1:0]<<YZeroCnt;
 
   
-  assign SqrtX = Xe[0] ? {3'b110, ~XZero, PreprocX} : {2'b11, ~XZero, PreprocX, 1'b0};
+  assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
-  assign X = Sqrt ? {SqrtX, {`DIVLEN-`NF{1'b0}}} : {3'b000, ~XZero, PreprocX, {`DIVLEN-`NF{1'b0}}};
+  assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
-  assign Dpreproc = {4'b0001, /*Int ? PreprocB : */PreprocY, {`DIVLEN-`NF{1'b0}}};
+  assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
   assign Dur = (`DURLEN)'(`FPDUR);
 
   //           radix 2     radix 4
@@ -99,7 +99,8 @@ module expcalc(
   output logic  [`NE+1:0] Qe
   );
   logic [`NE-2:0] Bias;
-  logic [`NE-1:0] SExp, SXExp;
+  logic [`NE+1:0] SXExp;
+  logic [`NE+1:0] SExp;
   logic [`NE+1:0] DExp;
   
   if (`FPSIZES == 1) begin
@@ -126,10 +127,10 @@ module expcalc(
             2'h2: Bias =  (`NE-1)'(`H_BIAS);
         endcase
   end
-  assign SXExp = Xe - (`NE)'(`BIAS);
+  assign SXExp = {2'b0, Xe} - {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, XZeroCnt} - (`NE+1)'(`BIAS);
-  assign SExp  = {1'b0, SXExp[`NE-1:1]} + Bias;
+  assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
   // correct exponent for denormalized input's normalization shifts
   assign DExp = ({2'b0, Xe} - {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, XZeroCnt} - {2'b0, Ye} + {{`NE+1-$unsigned($clog2(`NF+2)){1'b0}}, YZeroCnt} + {3'b0, Bias})&{`NE+2{~XZero}};
   
-  assign Qe = Sqrt ? {2'b0, SExp} : DExp;
+  assign Qe = Sqrt ? SExp : DExp;
 endmodule

pipelined/srt/inttestgen.c

@@ -8,7 +8,7 @@
 /* #includes */
 
 #include <stdio.h>
-#include <stdlib.h>
+#include <stdlib.h> 
 #include <math.h>
 
 /* Constants */

pipelined/testbench/testbench-fp.sv

@@ -80,7 +80,7 @@ module testbenchfp;
   logic CvtResSgnE;
   logic [`NE:0]           CvtCalcExpE;    // the calculated expoent
 	logic [`LOGCVTLEN-1:0] CvtShiftAmtE;  // how much to shift by
-	logic [`QLEN-1-(`RADIX/4):0] Quot;
+	logic [`DIVb-(`RADIX/4):0] Quot;
   logic CvtResDenormUfE;
   logic [`DURLEN-1:0] EarlyTermShift;
   logic DivStart, DivBusy;
@@ -256,16 +256,16 @@ module testbenchfp;
             Fmt = {Fmt, 2'b11};
           end
       end
-      // if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tested
+      if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tested
-      //   // add the square-root tests/op-ctrls/unit/fmt
+        // add the square-root tests/op-ctrls/unit/fmt
-      //   Tests = {Tests, f128sqrt};
+        Tests = {Tests, f128sqrt};
-      //   OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-      //   WriteInt = {WriteInt, 1'b0};
+        WriteInt = {WriteInt, 1'b0};
-      //     for(int i = 0; i<5; i++) begin
+          for(int i = 0; i<5; i++) begin
-      //       Unit = {Unit, `DIVUNIT};
+            Unit = {Unit, `DIVUNIT};
-      //       Fmt = {Fmt, 2'b11};
+            Fmt = {Fmt, 2'b11};
-      //     end
+          end
-      // end
+      end
       if (TEST === "fma"   | TEST === "all") begin  // if fused-mutliply-add is being tested
         Tests = {Tests, f128fma};
         OpCtrl = {OpCtrl, `FMA_OPCTRL};
@@ -383,16 +383,16 @@ module testbenchfp;
           Fmt = {Fmt, 2'b01};
         end
       end
-      // if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tessted
+      if (TEST === "sqrt"  | TEST === "all") begin // if square-root is being tessted
-      //   // add the correct tests/op-ctrls/unit/fmt to their lists
+        // add the correct tests/op-ctrls/unit/fmt to their lists
-      //   Tests = {Tests, f64sqrt};
+        Tests = {Tests, f64sqrt};
-      //   OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-      //   WriteInt = {WriteInt, 1'b0};
+        WriteInt = {WriteInt, 1'b0};
-      //   for(int i = 0; i<5; i++) begin
+        for(int i = 0; i<5; i++) begin
-      //     Unit = {Unit, `DIVUNIT};
+          Unit = {Unit, `DIVUNIT};
-      //     Fmt = {Fmt, 2'b01};
+          Fmt = {Fmt, 2'b01};
-      //   end
+        end
-      // end
+      end
       if (TEST === "fma"   | TEST === "all") begin // if the fused multiply add is being tested
         Tests = {Tests, f64fma};
         OpCtrl = {OpCtrl, `FMA_OPCTRL};
@@ -494,16 +494,16 @@ module testbenchfp;
           Fmt = {Fmt, 2'b00};
         end
       end
-      // if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
+      if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
-      //   // add the correct tests/op-ctrls/unit/fmt to their lists
+        // add the correct tests/op-ctrls/unit/fmt to their lists
-      //   Tests = {Tests, f32sqrt};
+        Tests = {Tests, f32sqrt};
-      //   OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-      //   WriteInt = {WriteInt, 1'b0};
+        WriteInt = {WriteInt, 1'b0};
-      //   for(int i = 0; i<5; i++) begin
+        for(int i = 0; i<5; i++) begin
-      //     Unit = {Unit, `DIVUNIT};
+          Unit = {Unit, `DIVUNIT};
-      //     Fmt = {Fmt, 2'b00};
+          Fmt = {Fmt, 2'b00};
-      //   end
+        end
-      // end
+      end
       if (TEST === "fma"   | TEST === "all")  begin // if fma is being tested
         Tests = {Tests, f32fma};
         OpCtrl = {OpCtrl, `FMA_OPCTRL};
@@ -587,16 +587,16 @@ module testbenchfp;
           Fmt = {Fmt, 2'b10};
         end
       end
-      // if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
+      if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
-      //   // add the correct tests/op-ctrls/unit/fmt to their lists
+        // add the correct tests/op-ctrls/unit/fmt to their lists
-      //   Tests = {Tests, f16sqrt};
+        Tests = {Tests, f16sqrt};
-      //   OpCtrl = {OpCtrl, `SQRT_OPCTRL};
+        OpCtrl = {OpCtrl, `SQRT_OPCTRL};
-      //   WriteInt = {WriteInt, 1'b0};
+        WriteInt = {WriteInt, 1'b0};
-      //   for(int i = 0; i<5; i++) begin
+        for(int i = 0; i<5; i++) begin
-      //     Unit = {Unit, `DIVUNIT};
+          Unit = {Unit, `DIVUNIT};
-      //     Fmt = {Fmt, 2'b10};
+          Fmt = {Fmt, 2'b10};
-      //   end
+        end
-      // end
+      end
       if (TEST === "fma"   | TEST === "all") begin // if fma is being tested
         Tests = {Tests, f16fma};
         OpCtrl = {OpCtrl, `FMA_OPCTRL};
@@ -697,7 +697,7 @@ module testbenchfp;
   fcmp fcmp   (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, 
               .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes),
               .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
-  divsqrt divsqrt(.clk, .reset, .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(1'b0), .SqrtM(1'b0),
+  divsqrt divsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
                   .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), 
                   .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
                   .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone);
@@ -1007,40 +1007,72 @@ module readvectors (
           end
         endcase
       `DIVUNIT:
-        case (Fmt)
+        if(OpCtrl[0])
-          2'b11: begin       // quad
+          case (Fmt)
-            X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
+            2'b11: begin       // quad
-            Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
+              X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
-            Ans = TestVector[8+(`Q_LEN-1):8];
+              Ans = TestVector[8+(`Q_LEN-1):8];
-            if (~clk) #5;
+              if (~clk) #5;
-            DivStart = 1'b1; #10 // one clk cycle
+              DivStart = 1'b1; #10 // one clk cycle
-            DivStart = 1'b0;
+              DivStart = 1'b0;
-          end
+            end
-          2'b01:	if (`D_SUPPORTED)begin	  // double
+            2'b01:	if (`D_SUPPORTED)begin	  // double
-            X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
-            Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
-            Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+              if (~clk) #5;
-            if (~clk) #5;
+              DivStart = 1'b1; #10
-            DivStart = 1'b1; #10
+              DivStart = 1'b0;
-            DivStart = 1'b0;
+            end
-          end
+            2'b00:	if (`S_SUPPORTED)begin	  // single
-          2'b00:	if (`S_SUPPORTED)begin	  // single
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
-            X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
-            Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
+              if (~clk) #5;
-            Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+              DivStart = 1'b1; #10
-            if (~clk) #5;
+              DivStart = 1'b0;
-            DivStart = 1'b1; #10
+            end
-            DivStart = 1'b0;
+            2'b10:	begin	  // half
-          end
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
-          2'b10:	begin	  // half
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
-            X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
+              if (~clk) #5;
-            Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
+              DivStart = 1'b1; #10
-            Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+              DivStart = 1'b0;
-            if (~clk) #5;
+            end
-            DivStart = 1'b1; #10
+          endcase
-            DivStart = 1'b0;
+        else
-          end
+          case (Fmt)
-        endcase
+            2'b11: begin       // quad
+              X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)];
+              Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)];
+              Ans = TestVector[8+(`Q_LEN-1):8];
+              if (~clk) #5;
+              DivStart = 1'b1; #10 // one clk cycle
+              DivStart = 1'b0;
+            end
+            2'b01:	if (`D_SUPPORTED)begin	  // double
+              X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]};
+              Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]};
+              Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+            2'b00:	if (`S_SUPPORTED)begin	  // single
+              X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]};
+              Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]};
+              Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+            2'b10:	begin	  // half
+              X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]};
+              Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]};
+              Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]};
+              if (~clk) #5;
+              DivStart = 1'b1; #10
+              DivStart = 1'b0;
+            end
+          endcase
       `CMPUNIT:
         case (Fmt)        
           2'b11: begin       // quad
@@ -1259,7 +1291,7 @@ module readvectors (
   end
   
   assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]);
-  assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT));
+  assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0]));
   assign ZEn = (Unit == `FMAUNIT);
   
   unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,

pipelined/testbench/testbench.sv

@@ -179,7 +179,7 @@ logic [3:0] dummy;
       testadr = 0;
       testadrNoBase = 0;
       // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and  tests[0] == "2" refers to WallyRiscvArchTests 
-      riscofTest = tests[0] == "1"; // | tests[0] == "2"; 
+      riscofTest = tests[0] == "1" | tests[0] == "2"; 
       // fill memory with defined values to reduce Xs in simulation
       // Quick note the memory will need to be initialized.  The C library does not
       //  guarantee the  initialized reads.  For example a strcmp can read 6 byte

pipelined/testbench/tests.vh

@@ -34,7 +34,7 @@
 string tvpaths[] = '{
     "../../addins/imperas-riscv-tests/work/",
     "../../tests/riscof/work/riscv-arch-test/",
-    "../../tests/wally-riscv-arch-test/work/", //"../../tests/riscof/work/wally-riscv-arch-test/", //
+    "../../tests/riscof/work/wally-riscv-arch-test/",
     "../../tests/imperas-riscv-tests/work/",
     "../../benchmarks/coremark/work/",
     "../../addins/embench-iot/"
@@ -92,24 +92,8 @@ string tvpaths[] = '{
     "bd_sizeopt_speed/src/wikisort/wikisort"
   };
 
-  string wally64a[] = '{
-    `WALLYTEST,
-    "rv64i_m/privilege/WALLY-amo",
-    "rv64i_m/privilege/WALLY-lrsc",
-    "rv64i_m/privilege/WALLY-status-fp-enabled-01"
-  };
-
-    string wally32a[] = '{
-    `WALLYTEST,
-    "rv32i_m/privilege/WALLY-amo",
-    "rv32i_m/privilege/WALLY-lrsc",
-    "rv32i_m/privilege/WALLY-status-fp-enabled-01"
-
-  };
-
   // *** restore CSR tests from Imperas old
-
+  string extra64i[] = '{
-    string extra64i[] = '{
     `MYIMPERASTEST,
     "rv64i_m/I/WALLY-ADD",
     "rv64i_m/I/WALLY-SUB",
@@ -919,6 +903,20 @@ string imperas32f[] = '{
     "rv32p/WALLY-CSR-PERMISSIONS-S"
   };
 
+ string wally64a[] = '{
+    `WALLYTEST,
+    "rv64i_m/privilege/src/WALLY-amo.S",
+    "rv64i_m/privilege/src/WALLY-lrsc.S",
+    "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S"
+  };
+
+ string wally32a[] = '{
+    `WALLYTEST,
+    "rv32i_m/privilege/src/WALLY-amo.S",
+    "rv32i_m/privilege/src/WALLY-lrsc.S",
+    "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S"
+ };
+
   string arch64priv[] = '{
     `RISCVARCHTEST,
     "rv64i_m/privilege/src/ebreak.S",
@@ -1491,212 +1489,126 @@ string imperas32f[] = '{
 
  string wally64i[] = '{
     `WALLYTEST,
-    "rv64i_m/I/WALLY-ADD",
+    "rv64i_m/I/src/WALLY-ADD.S",
-    "rv64i_m/I/WALLY-SLT",
+    "rv64i_m/I/src/WALLY-SLT.S",
-    "rv64i_m/I/WALLY-SLTU",
+    "rv64i_m/I/src/WALLY-SLTU.S",
-    "rv64i_m/I/WALLY-SUB",
+    "rv64i_m/I/src/WALLY-SUB.S",
-    "rv64i_m/I/WALLY-XOR"
+    "rv64i_m/I/src/WALLY-XOR.S"
  };
 
+ 
  string wally64priv[] = '{
     `WALLYTEST,
-    "rv64i_m/privilege/WALLY-status-tw-01",
+    "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
-    "rv64i_m/privilege/WALLY-csr-permission-s-01",
+    "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
-    "rv64i_m/privilege/WALLY-csr-permission-u-01",
+    "rv64i_m/privilege/src/WALLY-mie-01.S",
-    "rv64i_m/privilege/WALLY-minfo-01",
+    "rv64i_m/privilege/src/WALLY-minfo-01.S",
-    "rv64i_m/privilege/WALLY-misa-01",
+    "rv64i_m/privilege/src/WALLY-misa-01.S",
-    "rv64i_m/privilege/WALLY-mmu-sv39",
+    "rv64i_m/privilege/src/WALLY-mmu-sv39.S",
-    "rv64i_m/privilege/WALLY-mmu-sv48",
+    "rv64i_m/privilege/src/WALLY-mmu-sv48.S",
-    "rv64i_m/privilege/WALLY-pma",
+    "rv64i_m/privilege/src/WALLY-mtvec-01.S",
-    "rv64i_m/privilege/WALLY-pmp",
+    "rv64i_m/privilege/src/WALLY-pma.S",
-    "rv64i_m/privilege/WALLY-trap-01",
+    "rv64i_m/privilege/src/WALLY-pmp.S",
-    "rv64i_m/privilege/WALLY-trap-s-01",
+    "rv64i_m/privilege/src/WALLY-sie-01.S",
-    "rv64i_m/privilege/WALLY-trap-u-01",
+    "rv64i_m/privilege/src/WALLY-status-mie-01.S",
-    "rv64i_m/privilege/WALLY-mie-01",
+    "rv64i_m/privilege/src/WALLY-status-sie-01.S",
-    "rv64i_m/privilege/WALLY-sie-01",
+    "rv64i_m/privilege/src/WALLY-status-tw-01.S",
-    "rv64i_m/privilege/WALLY-mtvec-01",
+    "rv64i_m/privilege/src/WALLY-stvec-01.S",
-    "rv64i_m/privilege/WALLY-stvec-01",
+    "rv64i_m/privilege/src/WALLY-trap-01.S",
-    "rv64i_m/privilege/WALLY-status-mie-01",
+    "rv64i_m/privilege/src/WALLY-trap-s-01.S",
-    "rv64i_m/privilege/WALLY-status-sie-01",
+    "rv64i_m/privilege/src/WALLY-trap-sret-01.S",
-    "rv64i_m/privilege/WALLY-trap-sret-01",
+    "rv64i_m/privilege/src/WALLY-trap-u-01.S",
-    "rv64i_m/privilege/WALLY-status-tw-01",
+    "rv64i_m/privilege/src/WALLY-wfi-01.S"
-    "rv64i_m/privilege/WALLY-wfi-01"
  };
 
  string wally64periph[] = '{
     `WALLYTEST,
-    "rv64i_m/privilege/WALLY-periph"
+    "rv64i_m/privilege/src/WALLY-periph.S"
  };
 
  string wally32e[] = '{
     `WALLYTEST,
-    "rv32i_m/I/E-add-01",
+    "rv32i_m/I/src/E-add-01.S",
-    "rv32i_m/I/E-addi-01",
+    "rv32i_m/I/src/E-addi-01.S",
-    "rv32i_m/I/E-and-01",
+    "rv32i_m/I/src/E-and-01.S",
-    "rv32i_m/I/E-andi-01",
+    "rv32i_m/I/src/E-andi-01.S",
-    "rv32i_m/I/E-auipc-01",
+    "rv32i_m/I/src/E-auipc-01.S",
-    "rv32i_m/I/E-bge-01",
+    "rv32i_m/I/src/E-bge-01.S",
-    "rv32i_m/I/E-bgeu-01",
+    "rv32i_m/I/src/E-bgeu-01.S",
-    "rv32i_m/I/E-blt-01",
+    "rv32i_m/I/src/E-blt-01.S",
-    "rv32i_m/I/E-bltu-01",
+    "rv32i_m/I/src/E-bltu-01.S",
-    "rv32i_m/I/E-bne-01",
+    "rv32i_m/I/src/E-bne-01.S",
-    "rv32i_m/I/E-jal-01",
+    "rv32i_m/I/src/E-jal-01.S",
-    "rv32i_m/I/E-jalr-01",
+    "rv32i_m/I/src/E-jalr-01.S",
-    "rv32i_m/I/E-lb-align-01",
+    "rv32i_m/I/src/E-lb-align-01.S",
-    "rv32i_m/I/E-lbu-align-01",
+    "rv32i_m/I/src/E-lbu-align-01.S",
-    "rv32i_m/I/E-lh-align-01",
+    "rv32i_m/I/src/E-lh-align-01.S",
-    "rv32i_m/I/E-lhu-align-01",
+    "rv32i_m/I/src/E-lhu-align-01.S",
-    "rv32i_m/I/E-lui-01",
+    "rv32i_m/I/src/E-lui-01.S",
-    "rv32i_m/I/E-lw-align-01",
+    "rv32i_m/I/src/E-lw-align-01.S",
-    "rv32i_m/I/E-or-01",
+    "rv32i_m/I/src/E-or-01.S",
-    "rv32i_m/I/E-ori-01",
+    "rv32i_m/I/src/E-ori-01.S",
-    "rv32i_m/I/E-sb-align-01",
+    "rv32i_m/I/src/E-sb-align-01.S",
-    "rv32i_m/I/E-sh-align-01",
+    "rv32i_m/I/src/E-sh-align-01.S",
-    "rv32i_m/I/E-sll-01",
+    "rv32i_m/I/src/E-sll-01.S",
-    "rv32i_m/I/E-slli-01",
+    "rv32i_m/I/src/E-slli-01.S",
-    "rv32i_m/I/E-slt-01",
+    "rv32i_m/I/src/E-slt-01.S",
-    "rv32i_m/I/E-slti-01",
+    "rv32i_m/I/src/E-slti-01.S",
-    "rv32i_m/I/E-sltiu-01",
+    "rv32i_m/I/src/E-sltiu-01.S",
-    "rv32i_m/I/E-sltu-01",
+    "rv32i_m/I/src/E-sltu-01.S",
-    "rv32i_m/I/E-sra-01",
+    "rv32i_m/I/src/E-sra-01.S",
-    "rv32i_m/I/E-srai-01",
+    "rv32i_m/I/src/E-srai-01.S",
-    "rv32i_m/I/E-srl-01",
+    "rv32i_m/I/src/E-srl-01.S",
-    "rv32i_m/I/E-srli-01",
+    "rv32i_m/I/src/E-srli-01.S",
-    "rv32i_m/I/E-sub-01",
+    "rv32i_m/I/src/E-sub-01.S",
-    "rv32i_m/I/E-sw-align-01",
+    "rv32i_m/I/src/E-sw-align-01.S",
-    "rv32i_m/I/E-xor-01",
+    "rv32i_m/I/src/E-xor-01.S",
-    "rv32i_m/I/E-xori-01"
+    "rv32i_m/I/src/E-xori-01.S"
  };
 
-string wally32i[] = '{
+ string wally32i[] = '{
     `WALLYTEST,
-    "rv32i_m/I/WALLY-ADD",
+    "rv32i_m/I/src/WALLY-ADD.S",
-    "rv32i_m/I/WALLY-SLT",
+    "rv32i_m/I/src/WALLY-SLT.S",
-    "rv32i_m/I/WALLY-SLTU",
+    "rv32i_m/I/src/WALLY-SLTU.S",
-    "rv32i_m/I/WALLY-SUB",
+    "rv32i_m/I/src/WALLY-SUB.S",
-    "rv32i_m/I/WALLY-XOR"
+    "rv32i_m/I/src/WALLY-XOR.S" 
  };
 
+
  string wally32priv[] = '{
     `WALLYTEST,
-    "rv32i_m/privilege/WALLY-csr-permission-s-01",
+    "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
-    "rv32i_m/privilege/WALLY-csr-permission-u-01",
+    "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
-    "rv32i_m/privilege/WALLY-minfo-01",
+    "rv32i_m/privilege/src/WALLY-mie-01.S",
-    "rv32i_m/privilege/WALLY-misa-01",
+    "rv32i_m/privilege/src/WALLY-minfo-01.S",
-    "rv32i_m/privilege/WALLY-mmu-sv32",
+    "rv32i_m/privilege/src/WALLY-misa-01.S",
-    "rv32i_m/privilege/WALLY-pma",
+    "rv32i_m/privilege/src/WALLY-mmu-sv32.S",
-    "rv32i_m/privilege/WALLY-pmp",
+    "rv32i_m/privilege/src/WALLY-mtvec-01.S",
-    "rv32i_m/privilege/WALLY-trap-01",
+    "rv32i_m/privilege/src/WALLY-pma.S",
-    "rv32i_m/privilege/WALLY-trap-s-01",
+    "rv32i_m/privilege/src/WALLY-pmp.S",
-    "rv32i_m/privilege/WALLY-trap-u-01",
+    "rv32i_m/privilege/src/WALLY-sie-01.S",
-    "rv32i_m/privilege/WALLY-mie-01",
+    "rv32i_m/privilege/src/WALLY-status-mie-01.S",
-    "rv32i_m/privilege/WALLY-sie-01",
+    "rv32i_m/privilege/src/WALLY-status-sie-01.S",
-    "rv32i_m/privilege/WALLY-mtvec-01",
+    "rv32i_m/privilege/src/WALLY-status-tw-01.S",
-    "rv32i_m/privilege/WALLY-stvec-01",
+    "rv32i_m/privilege/src/WALLY-stvec-01.S",
-    "rv32i_m/privilege/WALLY-status-mie-01",
+    "rv32i_m/privilege/src/WALLY-trap-01.S",
-    "rv32i_m/privilege/WALLY-status-sie-01",
+    "rv32i_m/privilege/src/WALLY-trap-s-01.S",
-    "rv32i_m/privilege/WALLY-trap-sret-01",
+    "rv32i_m/privilege/src/WALLY-trap-sret-01.S",
-    "rv32i_m/privilege/WALLY-status-tw-01", 
+    "rv32i_m/privilege/src/WALLY-trap-u-01.S",
-    "rv32i_m/privilege/WALLY-wfi-01"
+    "rv32i_m/privilege/src/WALLY-wfi-01.S"
  };
 
  string wally32periph[] = '{
     `WALLYTEST,
-    "rv32i_m/privilege/WALLY-gpio-01",
+    "rv32i_m/privilege/src/WALLY-gpio-01.S",
-    "rv32i_m/privilege/WALLY-clint-01",
+    "rv32i_m/privilege/src/WALLY-clint-01.S",
-    "rv32i_m/privilege/WALLY-plic-01",
+    "rv32i_m/privilege/src/WALLY-uart-01.S",
-    "rv32i_m/privilege/WALLY-uart-01"
+    "rv32i_m/privilege/src/WALLY-plic-01.S"
  };
 
 
-// riscof test paths, to replace existing paths once riscof flow is working
-// string wally64a[] = '{
-//     `WALLYTEST,
-//     "rv64i_m/privilege/src/WALLY-amo.S",
-//     "rv64i_m/privilege/src/WALLY-lrsc.S",
-//     "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S"
-//   };
-
-//     string wally32a[] = '{
-//     `WALLYTEST,
-//     "rv32i_m/privilege/src/WALLY-amo.S",
-//     "rv32i_m/privilege/src/WALLY-lrsc.S",
-//     "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S"
-
-//   };
-
-//   string wally64i[] = '{
-//     `WALLYTEST,
-//     "rv64i_m/I/src/WALLY-ADD.S",
-//     "rv64i_m/I/src/WALLY-SLT.S",
-//     "rv64i_m/I/src/WALLY-SLTU.S",
-//     "rv64i_m/I/src/WALLY-SUB.S",
-//     "rv64i_m/I/src/WALLY-XOR.S"
-//  };
-
-//  string wally64priv[] = '{
-//     `WALLYTEST,
-//     "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
-//     "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
-//     "rv64i_m/privilege/src/WALLY-mie-01.S",
-//     "rv64i_m/privilege/src/WALLY-minfo-01.S",
-//     "rv64i_m/privilege/src/WALLY-misa-01.S",
-//     "rv64i_m/privilege/src/WALLY-mmu-sv39.S",
-//     "rv64i_m/privilege/src/WALLY-mmu-sv48.S",
-//     "rv64i_m/privilege/src/WALLY-mtvec-01.S",
-//     "rv64i_m/privilege/src/WALLY-pma.S",
-//     "rv64i_m/privilege/src/WALLY-pmp.S",
-//     "rv64i_m/privilege/src/WALLY-sie-01.S",
-//     "rv64i_m/privilege/src/WALLY-status-mie-01.S",
-//     "rv64i_m/privilege/src/WALLY-status-sie-01.S",
-//     "rv64i_m/privilege/src/WALLY-status-tw-01.S",
-//     "rv64i_m/privilege/src/WALLY-stvec-01.S",
-//     "rv64i_m/privilege/src/WALLY-trap-01.S",
-//     "rv64i_m/privilege/src/WALLY-trap-s-01.S",
-//     "rv64i_m/privilege/src/WALLY-trap-sret-01.S",
-//     "rv64i_m/privilege/src/WALLY-trap-u-01.S",
-//     "rv64i_m/privilege/src/WALLY-wfi-01.S"
-//  };
-
-//  string wally64periph[] = '{
-//     `WALLYTEST,
-//     "rv64i_m/privilege/src/WALLY-periph.S"
-//  };
-
-
  string wally32d[] = '{
     `WALLYTEST,
     "rv32i_m/D/src/WALLY-fld.S"
- };
+ };
-
-//  string wally32i[] = '{
-//     `WALLYTEST,
-//     "rv32i_m/I/src/WALLY-ADD.S",
-//     "rv32i_m/I/src/WALLY-SLT.S",
-//     "rv32i_m/I/src/WALLY-SLTU.S",
-//     "rv32i_m/I/src/WALLY-SUB.S",
-//     "rv32i_m/I/src/WALLY-XOR.S" 
-//  };
-
-//  string wally32priv[] = '{
-//     `WALLYTEST,
-//     "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S",
-//     "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S",
-//     "rv32i_m/privilege/src/WALLY-mie-01.S",
-//     "rv32i_m/privilege/src/WALLY-minfo-01.S",
-//     "rv32i_m/privilege/src/WALLY-misa-01.S",
-//     "rv32i_m/privilege/src/WALLY-mmu-sv32.S",
-//     "rv32i_m/privilege/src/WALLY-mtvec-01.S",
-//     "rv32i_m/privilege/src/WALLY-pma.S",
-//     "rv32i_m/privilege/src/WALLY-pmp.S",
-//     "rv32i_m/privilege/src/WALLY-sie-01.S",
-//     "rv32i_m/privilege/src/WALLY-status-mie-01.S",
-//     "rv32i_m/privilege/src/WALLY-status-sie-01.S",
-//     "rv32i_m/privilege/src/WALLY-status-tw-01.S",
-//     "rv32i_m/privilege/src/WALLY-stvec-01.S",
-//     "rv32i_m/privilege/src/WALLY-trap-01.S",
-//     "rv32i_m/privilege/src/WALLY-trap-s-01.S",
-//     "rv32i_m/privilege/src/WALLY-trap-sret-01.S",
-//     "rv32i_m/privilege/src/WALLY-trap-u-01.S",
-//     "rv32i_m/privilege/src/WALLY-wfi-01.S"
-//  };

tests/riscof/Makefile

@@ -8,7 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test
 current_dir = $(shell pwd)
 XLEN    ?= 64
 
-all: root build_arch #build_wally memfile
+all: root build_rv32e build_wally build_arch 
 
 root:
 	mkdir -p $(work_dir)
@@ -25,14 +25,24 @@ fsd_fld_tempfix:
 
 build_arch: fsd_fld_tempfix
 	riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
-	rm -rf $(arch_workdir)/rv$(XLEN)i_m
+# rm -rf $(arch_workdir)/rv$(XLEN)i_m
 	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
 	rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
 
 build_wally:
-	riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
+	riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
-	rm -rf $(wally_workdir)/rv$(XLEN)i_m
+# riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
-	mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/
+# rm -rf $(wally_workdir)/rv$(XLEN)i_m
+# mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/
+	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
+	rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
+
+build_rv32e:
+	sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
+	riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+# riscof --verbose debug run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
+	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
+	rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
 
 memfile: 
 	find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done
@@ -42,6 +52,7 @@ memfile:
 clean:
 	rm -f config64.ini
 	rm -f config32.ini
+	rm -f config32e.ini
 	rm -rf $(work_dir)
 	rm -rf $(wally_workdir)
 	rm -rf $(arch_workdir)

tests/riscof/sail_cSim/env/model_test.h

@@ -15,7 +15,7 @@
 #define RVMODEL_HALT                                              \
   li x1, 1;                                                                   \
   write_tohost:                                                               \
-    sw x1, tohost, t5;                                                        \
+    sw x1, tohost, t0;                                                        \
     j write_tohost;
 
 #define RVMODEL_BOOT

tests/riscof/sail_cSim/riscof_sail_cSim.py

@@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate):
         ispec = utils.load_yaml(isa_yaml)['hart0']
         self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
         self.isa = 'rv' + self.xlen
-        self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ')
+        self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
         if "I" in ispec["ISA"]:
             self.isa += 'i'
         if "M" in ispec["ISA"]:
@@ -100,8 +100,14 @@ class sail_cSim(pluginTemplate):
 
             execute += self.objdump_cmd.format(elf, self.xlen, 'ref.elf.objdump')
             sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
-
+            
-            execute += self.sail_exe[self.xlen] + ' -z268435455 --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
+            # Check if the tests can be run on SAIL
+            if ('NO_SAIL=True' in testentry['macros']):
+                # if the tests can't run on SAIL we copy the reference output to the src directory
+                reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
+                execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
+            else:
+                execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
 
             cov_str = ' '
             for label in testentry['coverage_labels']:

tests/riscof/spike/env/model_test.h

@@ -14,7 +14,7 @@
 #define RVMODEL_HALT                                              \
   li x1, 1;                                                                   \
   write_tohost:                                                               \
-    sw x1, tohost, t5;                                                        \
+    sw x1, tohost, t0;                                                        \
     j write_tohost;
 
 #define RVMODEL_BOOT

tests/riscof/spike/spike_rv32e_isa.yaml

@@ -0,0 +1,29 @@
+hart_ids: [0]
+hart0:
+  ISA: RV32EMFCZicsr_Zifencei
+  physical_addr_sz: 32
+  User_Spec_Version: '2.3'
+  supported_xlen: [32]
+  misa:
+   reset-val: 0x40001034
+   rv32:
+     accessible: true
+     mxl:
+       implemented: true
+       type:
+           warl:
+              dependency_fields: []
+              legal:
+                - mxl[1:0] in [0x1]
+              wr_illegal:
+                - Unchanged
+     extensions:
+       implemented: true
+       type:
+           warl:
+              dependency_fields: []
+              legal:
+                - extensions[25:0] bitmask [0x0001034, 0x0000000]
+              wr_illegal:
+                - Unchanged
+ 

tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h

@@ -11,7 +11,7 @@
 //   #define rvtest_gpr_save
 // #endif
 
-#define TEST_CASE_1
+// #define TEST_CASE_1
 
 //-----------------------------------------------------------------------
 // RV Arch Test Macros
@@ -95,14 +95,14 @@
   #endif
 #endif
 
-#if XLEN==64
+// #if XLEN==64
-  #if FLEN==32
+//   #if FLEN==32
-    #define SREG sw
+//     #define SREG sw
-    #define LREG lW
+//     #define LREG lW
-    #define REGWIDTH 4
+//     #define REGWIDTH 4
-    #define MASK 0xFFFFFFFF
+//     #define MASK 0xFFFFFFFF
-  #endif
+//   #endif
-#endif
+// #endif
 
 #define MMODE_SIG 3
 #define RLENG (REGWIDTH<<3)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -27,6 +28,7 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
 
 # Testcase 0:  rs1:x28(0x00000000), rs2:x13(0x00000000), result rd:x25(0x00000000)
 li x28, MASK_XLEN(0x00000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt)
+
 # Testcase 0:  rs1:x11(0x00000000), rs2:x8(0x00000000), result rd:x24(0x00000000)
 li x11, MASK_XLEN(0x00000000)
 li x8, MASK_XLEN(0x00000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu)
+
 # Testcase 0:  rs1:x20(0x00000000), rs2:x26(0x00000000), result rd:x13(0x00000000)
 li x20, MASK_XLEN(0x00000000)
 li x26, MASK_XLEN(0x00000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -26,6 +27,8 @@ rvtest_entry_point:
 RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub)
+
 RVTEST_SIGBASE( x6, wally_signature)
 
 # Testcase 0:  rs1:x3(0x00000000), rs2:x29(0x00000000), result rd:x28(0x00000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor)
+
 # Testcase 0:  rs1:x14(0x00000000), rs2:x19(0x00000000), result rd:x9(0x00000000)
 li x14, MASK_XLEN(0x00000000)
 li x19, MASK_XLEN(0x00000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output

@@ -6,16 +6,16 @@
 00000000 # mtval of faulting instruction (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000003 # mcause from Breakpoint
-80000168 # mtval of breakpoint instruction adress
+8000015c # mtval of breakpoint instruction adress
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000004 # mcause from load address misaligned
-80000171 # mtval of misaligned address
+80000165 # mtval of misaligned address
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000005 # mcause from load access
 00000000 # mtval of accessed adress (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000006 # mcause from store misaligned
-80000189 # mtval of address with misaligned store instr
+8000017d # mtval of address with misaligned store instr
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000007 # mcause from store access
 00000000 # mtval of accessed address (0x0)
@@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
 00000000 # mtval of faulting instruction (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000003 # mcause from Breakpoint
-80000168 # mtval of breakpoint instruction adress
+8000015c # mtval of breakpoint instruction adress
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000004 # mcause from load address misaligned
-80000171 # mtval of misaligned address
+80000165 # mtval of misaligned address
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000005 # mcause from load access
 00000000 # mtval of accessed adress (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000006 # mcause from store misaligned
-80000189 # mtval of address with misaligned store instr
+8000017d # mtval of address with misaligned store instr
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000007 # mcause from store access
 00000000 # mtval of accessed address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output

@@ -9,16 +9,16 @@
 00000000 # stval of faulting instruction (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -64,16 +64,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
 00000000 # stval of faulting instruction (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output

@@ -9,16 +9,16 @@
 00000000 # stval of faulting instruction (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)
@@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
 00000000 # stval of faulting instruction (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000003 # scause from Breakpoint
-80000168 # stval of breakpoint instruction adress
+8000015c # stval of breakpoint instruction adress
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000004 # scause from load address misaligned
-80000171 # stval of misaligned address
+80000165 # stval of misaligned address
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000005 # scause from load access
 00000000 # stval of accessed adress (0x0)
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000006 # scause from store misaligned
-80000189 # stval of address with misaligned store instr
+8000017d # stval of address with misaligned store instr
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000007 # scause from store access
 00000000 # stval of accessed address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -26,7 +26,7 @@
 
 .macro INIT_TESTS
 
-RVTEST_ISA("RV32I")
+// RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -152,7 +152,15 @@ cause_s_soft_interrupt:
     csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
     ret
 
+cause_s_soft_from_m_interrupt:
+    li t3, 0x2
+    csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
+    ret
+
 cause_m_ext_interrupt:
+    // these interrupts involve a time loop waiting for the interrupt to go off.
+    // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
+    li a3, 0x40
     // ========== Configure PLIC ==========
     // m priority threshold = 0
     li t3, 0xC200000
@@ -189,6 +197,9 @@ m_ext_loop:
     ret
 
 cause_s_ext_interrupt_GPIO:
+    // these interrupts involve a time loop waiting for the interrupt to go off.
+    // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
+    li a3, 0x40
     // ========== Configure PLIC ==========
     // s priority threshold = 0
     li t3, 0xC201000

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S

@@ -24,7 +24,8 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV32IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",amo)
 
 .section .text.init
 .globl rvtest_entry_point

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-32.h" 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S

@@ -24,7 +24,8 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV32IA")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",lrsc)
 
 .section .text.init
 .globl rvtest_entry_point

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mie)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",mmu)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mtvec)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S

@@ -36,6 +36,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
+
 INIT_TESTS
 
 TRAP_HANDLER m
@@ -54,6 +57,8 @@ test_cases:
 
 # Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below
 
+.4byte 0x80100300, 0xFEEDBEEF, write32_test
+
 # write pmpaddr regs
                                          # | Reg   | pmpaddr     | pmpcfg    | L | A     | X | W | R | Comments 		                |
 .4byte 0x0, 0x0FFFFFFF, write_pmpaddr_0  # | 0     | 0x0FFFFFFF  | 1F        | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW 		|

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",sie)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
@@ -43,7 +46,7 @@ WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
 jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending
 GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out.
 jal cause_s_soft_interrupt
-li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
+# li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
 // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
 jal cause_s_ext_interrupt_GPIO
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S

@@ -23,8 +23,15 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
+
 INIT_TESTS
 
+// Set the FS bits to 01, This makes sure SAILs mstatus matches wally in the signature
+li x29, 0x00002000 
+csrw mstatus, x29 
+
 TRAP_HANDLER m
 
 // Misa.F is already 1 in this config, making floating point enabled

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-mie)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S

@@ -24,6 +24,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tw)
+
 INIT_TESTS
 
 TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",stvec)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
@@ -48,7 +51,7 @@ GOTO_S_MODE // Causes U mode ecall
 GOTO_M_MODE // Causes S mode ecall
 
 
-jal cause_s_soft_interrupt 
+jal cause_s_soft_from_m_interrupt 
 jal cause_m_soft_interrupt
 jal cause_s_time_interrupt
 jal cause_m_time_interrupt
@@ -70,14 +73,11 @@ jal cause_store_addr_misaligned
 jal cause_store_acc
 jal cause_ecall // M mode ecall
 
-jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
+jal cause_s_soft_from_m_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
 jal cause_m_soft_interrupt
 jal cause_s_time_interrupt 
 jal cause_m_time_interrupt
-li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
-// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
 jal cause_s_ext_interrupt_GPIO
-li a3, 0x40
 jal cause_m_ext_interrupt
 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def NO_SAIL=True;",trap-s)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
+
 INIT_TESTS
 
 TRAP_HANDLER m, EXT_SIGNATURE=1

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
+
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-32.h"
 
+RVTEST_ISA("RV32I")
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
+
 INIT_TESTS
 
 TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
+
 # Testcase 0:  rs1:x20(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x3(0x0000000000000000)
 li x20, MASK_XLEN(0x0000000000000000)
 li x22, MASK_XLEN(0x0000000000000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt)
+
 # Testcase 0:  rs1:x18(0x0000000000000000), rs2:x9(0x0000000000000000), result rd:x5(0x0000000000000000)
 li x18, MASK_XLEN(0x0000000000000000)
 li x9, MASK_XLEN(0x0000000000000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu)
+
 # Testcase 0:  rs1:x22(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x2(0x0000000000000000)
 li x22, MASK_XLEN(0x0000000000000000)
 li x23, MASK_XLEN(0x0000000000000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub)
+
 # Testcase 0:  rs1:x4(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x13(0x0000000000000000)
 li x4, MASK_XLEN(0x0000000000000000)
 li x23, MASK_XLEN(0x0000000000000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S

@@ -19,6 +19,7 @@
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN
 
 RVTEST_SIGBASE( x6, wally_signature)
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor)
+
 # Testcase 0:  rs1:x27(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x17(0x0000000000000000)
 li x27, MASK_XLEN(0x0000000000000000)
 li x22, MASK_XLEN(0x0000000000000000)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output

@@ -14,13 +14,13 @@
 00000000
 00000003 # mcause from Breakpoint
 00000000
-80000400 # mtval of breakpoint instruction adress (0x80000400)
+800003f4 # mtval of breakpoint instruction adress (0x80000400)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-80000409 # mtval of misaligned address (0x80000409)
+800003fd # mtval of misaligned address (0x80000409)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -32,7 +32,7 @@
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000421 # mtval of address with misaligned store instr (0x80000421)
+80000415 # mtval of address with misaligned store instr (0x80000421)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -126,13 +126,13 @@ ffffffff
 00000000
 00000003 # mcause from Breakpoint
 00000000
-80000400 # mtval of breakpoint instruction adress (0x80000400)
+800003f4 # mtval of breakpoint instruction adress (0x80000400)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-80000409 # mtval of misaligned address (0x80000409)
+800003fd # mtval of misaligned address (0x80000409)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -144,7 +144,7 @@ ffffffff
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000421 # mtval of address with misaligned store instr (0x80000421)
+80000415 # mtval of address with misaligned store instr (0x80000421)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output

@@ -20,13 +20,13 @@
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000400 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-80000409 # stval of misaligned address (0x80000409)
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -38,7 +38,7 @@
 00000000
 00000006 # scause from store misaligned
 00000000
-80000421 # stval of address with misaligned store instr (0x80000421)
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -130,13 +130,13 @@ ffffffff
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000400 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-80000409 # stval of misaligned address (0x80000409)
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -148,7 +148,7 @@ ffffffff
 00000000
 00000006 # scause from store misaligned
 00000000
-80000421 # stval of address with misaligned store instr (0x80000421)
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output

@@ -20,13 +20,13 @@
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000400 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-80000409 # stval of misaligned address (0x80000409)
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -38,7 +38,7 @@
 00000000
 00000006 # scause from store misaligned
 00000000
-80000421 # stval of address with misaligned store instr (0x80000421)
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
@@ -116,13 +116,13 @@ ffffffff
 00000000
 00000003 # scause from Breakpoint
 00000000
-80000400 # stval of breakpoint instruction adress (0x80000400)
+800003f4 # stval of breakpoint instruction adress (0x80000400)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
 00000004 # scause from load address misaligned
 00000000
-80000409 # stval of misaligned address (0x80000409)
+800003fd # stval of misaligned address (0x80000409)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000
@@ -134,7 +134,7 @@ ffffffff
 00000000
 00000006 # scause from store misaligned
 00000000
-80000421 # stval of address with misaligned store instr (0x80000421)
+80000415 # stval of address with misaligned store instr (0x80000421)
 00000000
 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -26,7 +26,7 @@
 
 .macro INIT_TESTS
 
-RVTEST_ISA("RV64I")
+// RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -156,6 +156,7 @@ cause_s_soft_interrupt:
 
 cause_m_ext_interrupt:
     // ========== Configure PLIC ==========
+    li a3, 0x40
     // m priority threshold = 0
     li t3, 0xC200000
     li t4, 0
@@ -192,6 +193,7 @@ m_ext_loop:
 
 cause_s_ext_interrupt_GPIO:
     // ========== Configure PLIC ==========
+    li a3, 0x40
     // s priority threshold = 0
     li t3, 0xC201000
     li t4, 0

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S

@@ -24,7 +24,8 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True;",amo)
 
 .section .text.init
 .globl rvtest_entry_point

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S

@@ -23,6 +23,9 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u)
+
 INIT_TESTS
 
 TRAP_HANDLER m

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S

@@ -24,7 +24,8 @@
 #include "model_test.h"
 #include "arch_test.h"
 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True",lrsc)
 
 .section .text.init
 .globl rvtest_entry_point

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S

@@ -22,7 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
-
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mie)
 INIT_TESTS
 
 CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",mmu-sv39)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sv48)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",mtvec)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S

@@ -24,6 +24,8 @@
 #include "arch_test.h"
 
 RVTEST_ISA("RV64I")
+// this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph)
 
 .section .text.init
 .globl rvtest_entry_point

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S

@@ -35,6 +35,8 @@
 #define PLIC_RANGE     0x03FFFFFF
 
 #include "WALLY-TEST-LIB-64.h" 
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",sie)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S

@@ -22,9 +22,15 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64IAF")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled)
 
 INIT_TESTS
 
+// Set the FS bits to 01, This makes sure SAILs mstatus matches wally in the signature
+li x29, 0x00002000 
+csrw mstatus, x29 
+
 TRAP_HANDLER m
 
 // Misa.F is already 1 in this config, making floating point enabled

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-mie)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-sie)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S

@@ -23,6 +23,8 @@
 
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-tw)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",stvec)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap)
 
 INIT_TESTS
 
@@ -77,7 +79,6 @@ jal cause_m_time_interrupt
 li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
 // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
 jal cause_s_ext_interrupt_GPIO
-li a3, 0x40
 jal cause_m_ext_interrupt
 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-s)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-u)
 
 INIT_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S

@@ -22,6 +22,8 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h"
+RVTEST_ISA("RV64I")
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",wfi)
 
 INIT_TESTS