diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv
index 306463a62..5fc5d18e9 100644
--- a/src/privileged/csr.sv
+++ b/src/privileged/csr.sv
@@ -73,6 +73,8 @@ module csr #(parameter
   input  logic             ICacheAccess,
   input  logic             sfencevmaM,
   input  logic             FenceM,
+  input  logic             DivBusyE,                                  // integer divide busy
+  input  logic             FDivBusyE,                                 // floating point divide busy
   // outputs from CSRs
   output logic [1:0]       STATUS_MPP,
   output logic             STATUS_SPP, STATUS_TSR, STATUS_TVM,
@@ -266,7 +268,7 @@ module csr #(parameter
       .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
       .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
-      .InterruptM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM,
+      .InterruptM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
       .MTIME_CLINT,  .CSRCReadValM, .IllegalCSRCAccessM);
diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv
index bc2c2b963..feab9404f 100644
--- a/src/privileged/csrc.sv
+++ b/src/privileged/csrc.sv
@@ -61,6 +61,8 @@ module csrc #(parameter
   input  logic              InterruptM,
   input  logic              ExceptionM,
   input  logic              FenceM,
+  input  logic              DivBusyE,                                  // integer divide busy
+  input  logic              FDivBusyE,                                 // floating point divide busy
   input  logic [11:0] 	    CSRAdrM,
   input  logic [1:0] 	    PrivilegeModeW,
   input  logic [`XLEN-1:0]  CSRWriteValM,
@@ -113,7 +115,7 @@ module csrc #(parameter
     assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                       // sfence.vma
     assign CounterEvent[22] = InterruptM;                                               // interrupt, InstrValidNotFlushedM will be low
     assign CounterEvent[23] = ExceptionM;                                               // exceptions, InstrValidNotFlushedM will be low
-    assign CounterEvent[24] = '0;                                                       // ******** # division cycles
+    assign CounterEvent[24] = DivBusyE | FDivBusyE;                                     // division cycles *** RT: might need to be delay until the next cycle
     assign CounterEvent[`COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end
   
diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv
index 0a85d52db..fd4bb0f83 100644
--- a/src/privileged/privileged.sv
+++ b/src/privileged/privileged.sv
@@ -59,6 +59,8 @@ module privileged (
   input  logic             DCacheAccess,                              // data cache accessed (hit or miss)
   input  logic             ICacheMiss,                                // instruction cache miss
   input  logic             ICacheAccess,                              // instruction cache access
+  input  logic             DivBusyE,                                  // integer divide busy
+  input  logic             FDivBusyE,                                 // floating point divide busy
   // fault sources
   input  logic             InstrAccessFaultF,                         // instruction access fault
   input  logic             LoadAccessFaultM, StoreAmoAccessFaultM,    // load or store access fault
@@ -129,7 +131,7 @@ module privileged (
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
     .BPDirPredWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPWrongM,
-    .sfencevmaM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM,
+    .sfencevmaM, .ExceptionM, .FenceM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
     .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index 567d10e77..4e68ce481 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -292,7 +292,7 @@ module wallypipelinedcore (
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD, .StoreStallD,
       .BPDirPredWrongM, .BTBPredPCWrongM, .BPWrongM,
-      .RASPredPCWrongM, .IClassWrongM,
+      .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
       .InstrMisalignedFaultM, .IllegalIEUFPUInstrD,