Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Change busybear testbench to reflect new location of InstrF

Browse Source
This commit is contained in:
Jarred Allen 2021-03-20 18:20:27 -04:00
parent 097e8edb3d
commit 5b1db9b6a2
2 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/regression/wally-busybear.do
View File

@ -46,7 +46,7 @@ add wave -divider
add wave -hex /testbench_busybear/PCtext add wave -hex /testbench_busybear/PCtext
add wave -hex /testbench_busybear/pcExpected add wave -hex /testbench_busybear/pcExpected
add wave -hex /testbench_busybear/dut/hart/ifu/PCF add wave -hex /testbench_busybear/dut/hart/ifu/PCF
add wave -hex /testbench_busybear/dut/hart/ifu/InstrF add wave -hex /testbench_busybear/dut/hart/ifu/ic/InstrF
add wave -hex /testbench_busybear/dut/hart/ifu/StallD add wave -hex /testbench_busybear/dut/hart/ifu/StallD
add wave -hex /testbench_busybear/dut/hart/ifu/FlushD add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD

34
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -356,10 +356,10 @@ module testbench_busybear();
logic [31:0] InstrMask; logic [31:0] InstrMask;
logic forcedInstr; logic forcedInstr;
logic [63:0] lastPCF; logic [63:0] lastPCF;
always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin always @(dut.PCF or dut.hart.ifu.ic.InstrF or reset) begin
if(~HWRITE) begin if(~HWRITE) begin
#3; #3;
if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin if (~reset && dut.hart.ifu.ic.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
if (dut.PCF !== lastPCF) begin if (dut.PCF !== lastPCF) begin
lastCheckInstrF = CheckInstrF; lastCheckInstrF = CheckInstrF;
lastPC <= dut.PCF; lastPC <= dut.PCF;
@ -367,23 +367,23 @@ module testbench_busybear();
if (speculative && (lastPC != pcExpected)) begin if (speculative && (lastPC != pcExpected)) begin
speculative = ~equal(dut.PCF,pcExpected,3); speculative = ~equal(dut.PCF,pcExpected,3);
if(dut.PCF===pcExpected) begin if(dut.PCF===pcExpected) begin
if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs if(dut.hart.ifu.ic.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
force CheckInstrF = 32'b0010011; force CheckInstrF = 32'b0010011;
release CheckInstrF; release CheckInstrF;
force dut.hart.ifu.InstrF = 32'b0010011; force dut.hart.ifu.ic.InstrF = 32'b0010011;
#7; #7;
release dut.hart.ifu.InstrF; release dut.hart.ifu.ic.InstrF;
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
end end
else begin else begin
if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD if(dut.hart.ifu.ic.InstrF[28:27] != 2'b11 && dut.hart.ifu.ic.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
release CheckInstrF; release CheckInstrF;
force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011}; force dut.hart.ifu.ic.InstrF = {12'b0, dut.hart.ifu.ic.InstrF[19:7], 7'b0000011};
#7; #7;
release dut.hart.ifu.InstrF; release dut.hart.ifu.ic.InstrF;
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
@ -406,23 +406,23 @@ module testbench_busybear();
end end
scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF); scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
if(dut.PCF === pcExpected) begin if(dut.PCF === pcExpected) begin
if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs if(dut.hart.ifu.ic.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
force CheckInstrF = 32'b0010011; force CheckInstrF = 32'b0010011;
release CheckInstrF; release CheckInstrF;
force dut.hart.ifu.InstrF = 32'b0010011; force dut.hart.ifu.ic.InstrF = 32'b0010011;
#7; #7;
release dut.hart.ifu.InstrF; release dut.hart.ifu.ic.InstrF;
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time); $display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
end end
else begin else begin
if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD if(dut.hart.ifu.ic.InstrF[28:27] != 2'b11 && dut.hart.ifu.ic.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011}; force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
release CheckInstrF; release CheckInstrF;
force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011}; force dut.hart.ifu.ic.InstrF = {12'b0, dut.hart.ifu.ic.InstrF[19:7], 7'b0000011};
#7; #7;
release dut.hart.ifu.InstrF; release dut.hart.ifu.ic.InstrF;
$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF); $display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
warningCount += 1; warningCount += 1;
forcedInstr = 1; forcedInstr = 1;
@ -467,8 +467,8 @@ module testbench_busybear();
`ERROR `ERROR
end end
InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF; InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrF) !== (InstrMask & CheckInstrF))) begin if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.ic.InstrF) !== (InstrMask & CheckInstrF))) begin
$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrF, CheckInstrF, dut.PCF); $display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.ic.InstrF, CheckInstrF, dut.PCF);
`ERROR `ERROR
end end
end end
@ -481,7 +481,7 @@ module testbench_busybear();
// Track names of instructions // Track names of instructions
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;
instrNameDecTB dec(dut.hart.ifu.InstrF, InstrFName); instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
dut.hart.ifu.InstrM, InstrW, dut.hart.ifu.InstrM, InstrW,