diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index f20da4e22..8fe418272 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -276,7 +276,7 @@ cd "$RISCV" # Temporarily pin riscv-gnu-toolchain to use GCC 13.2.0. GCC 14 does not work with the Q extension. if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd "$RISCV"/riscv-gnu-toolchain - git reset --hard && git clean -f && git checkout master && git pull + git reset --hard && git clean -f && git checkout master && git pull && git submodule update ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then @@ -324,8 +324,7 @@ STATUS="qemu" cd "$RISCV" if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then cd "$RISCV"/qemu - git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}" - git submodule update --init --recursive + git reset --hard && git clean -f && git checkout master && git pull ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j "${NUM_THREADS}" 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] make install 2>&1 | logger $STATUS; [ "${PIPESTATUS[0]}" == 0 ] diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index eed513f9f..97496a8b9 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -10,13 +10,6 @@ `include "RV32M_coverage.svh" `include "RV32F_coverage.svh" `include "RV32D_coverage.svh" -`include "RV32Zba_coverage.svh" -`include "RV32Zbb_coverage.svh" -`include "RV32Zbc_coverage.svh" -`include "RV32Zbs_coverage.svh" -`include "RV32Zbkb_coverage.svh" -`include "RV32Zbkc_coverage.svh" -`include "RV32Zbkx_coverage.svh" `include "RV32ZfaF_coverage.svh" `include "RV32ZfaD_coverage.svh" `include "RV32ZfaZfh_coverage.svh" @@ -29,11 +22,6 @@ `include "RV32ZcbZbb_coverage.svh" `include "RV32Zcf_coverage.svh" `include "RV32Zcd_coverage.svh" -`include "RV32Zaamo_coverage.svh" -`include "RV32Zalrsc_coverage.svh" -`include "RV32Zknd_coverage.svh" -`include "RV32Zkne_coverage.svh" -`include "RV32Zknh_coverage.svh" // Privileged extensions `include "ZicsrM_coverage.svh" diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index a4b5fe64c..46d0d31c3 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -71,6 +71,7 @@ --override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions +--override show_c_prefix=T # Show "c." with compressed instructions # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index a293eb5b1..d54a342dd 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -10,16 +10,9 @@ `include "RV64M_coverage.svh" `include "RV64F_coverage.svh" `include "RV64D_coverage.svh" -`include "RV64Zba_coverage.svh" -`include "RV64Zbb_coverage.svh" -`include "RV64Zbc_coverage.svh" -`include "RV64Zbs_coverage.svh" -`include "RV64Zbkb_coverage.svh" -`include "RV64Zbkc_coverage.svh" -`include "RV64Zbkx_coverage.svh" `include "RV64ZfaF_coverage.svh" -`include "RV32ZfaD_coverage.svh" -`include "RV32ZfaZfh_coverage.svh" +`include "RV64ZfaD_coverage.svh" +`include "RV64ZfaZfh_coverage.svh" `include "RV64ZfhD_coverage.svh" `include "RV64Zfh_coverage.svh" `include "RV64Zicond_coverage.svh" @@ -29,18 +22,6 @@ `include "RV64ZcbZbb_coverage.svh" `include "RV64ZcbZba_coverage.svh" `include "RV64Zcd_coverage.svh" -`include "RV64Zaamo_coverage.svh" -`include "RV64Zalrsc_coverage.svh" -`include "RV64Zknd_coverage.svh" -`include "RV64Zkne_coverage.svh" -`include "RV64Zknh_coverage.svh" - - - - - - - // Privileged extensions `include "RV64VM_coverage.svh" diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 0ff19fa68..9ba14f2f0 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -70,6 +70,9 @@ # For code coverage, don't produce pseudoinstructions --override no_pseudo_inst=T +# Show "c." with compressed instructions +--override show_c_prefix=T + # nonratified mnosie register not implemented --override cpu/mnoise_undefined=T diff --git a/linux/Makefile b/linux/Makefile index b098b0a8b..85ef24ccb 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -60,7 +60,7 @@ install: check_write_permissions check_environment dumptvs: check_write_permissions check_environment $(SUDO) mkdir -p $(RISCV)/linux-testvectors - cd testvector-generation; ./genInitMem.sh + ./genInitMem.sh @echo "Testvectors successfully generated." generate: $(DTB) $(IMAGES) diff --git a/linux/bootmem.txt b/linux/bootmem.txt deleted file mode 100644 index 7cf7d8453..000000000 --- a/linux/bootmem.txt +++ /dev/null @@ -1,12 +0,0 @@ -00001000: 00000297 auipc t0, 0 # t0 = 0x00001000 -00001004: 02828613 addi a2, t0,0x28 # a2 = 0x00001028 -00001008: f1402573 csrr a0, mhartid # a0 = mhartid -0000100c: 0202b583 ld a1, 32(t0) # a1 = 87000000 - device tree address -00001010: 0182b283 ld t0, 24(t0) # t0 = 80000000 - start of firmware -00001014: 00028067 jr t0 # jump to firmware -00001018: 0000000080000000 # firmware start address -00001020: 000000008fe00000 # flattened device tree load address -00001028: 000000004942534f # a2 points to this 8 dword data structure -00001030: 0000000000000002 -00001038: 0000000080200000 -00001040: 0000000000000001 diff --git a/linux/testvector-generation/genInitMem.sh b/linux/genInitMem.sh similarity index 88% rename from linux/testvector-generation/genInitMem.sh rename to linux/genInitMem.sh index 1274a4240..a85837f80 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/genInitMem.sh @@ -46,9 +46,12 @@ echo "Launching QEMU in replay mode!" -ex "q" echo "Changing Endianness" -make fixBinMem -./fixBinMem "$rawRamFile" "$ramFile" -./fixBinMem "$rawBootmemFile" "$bootmemFile" +# Extend files to 8 byte multiple +truncate -s %8 "$rawRamFile" +truncate -s %8 "$rawBootmemFile" +# Reverse bytes +objcopy --reverse-bytes=8 -F binary "$rawRamFile" "$ramFile" +objcopy --reverse-bytes=8 -F binary "$rawBootmemFile" "$bootmemFile" rm -f "$rawRamFile" "$rawBootmemFile" "$rawUntrimmedBootmemFile" echo "genInitMem.sh completed!" diff --git a/linux/testvector-generation/Makefile b/linux/testvector-generation/Makefile deleted file mode 100644 index c31aae39d..000000000 --- a/linux/testvector-generation/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -SHELL = /bin/sh - -CFLAG = -Wall -g -CC = gcc - -all: fixBinMem - -fixBinMem: fixBinMem.c - ${CC} ${CFLAGS} fixBinMem.c -o fixBinMem - chmod +x fixBinMem - -clean: - -rm -f fixBinMem diff --git a/linux/testvector-generation/fixBinMem.c b/linux/testvector-generation/fixBinMem.c deleted file mode 100644 index fe071008b..000000000 --- a/linux/testvector-generation/fixBinMem.c +++ /dev/null @@ -1,33 +0,0 @@ -#include -#include -#include -int main(int argc, char *argv[]) { - if (argc < 3){ - fprintf(stderr, "Expected 2 arguments: \n"); - exit(1); - } - char* rawGDBfilePath = argv[1]; - FILE* rawGDBfile; - if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) { - fprintf(stderr, "File not found: %s\n",rawGDBfilePath); - exit(1); - } - char* outFilePath = argv[2]; - FILE* outFile = fopen(outFilePath,"w"); - uint64_t qemuWord; - uint64_t verilogWord; - int bytesReturned=0; - do { - bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile); - verilogWord = (((qemuWord>>0 )&0xff)<<56 | - ((qemuWord>>8 )&0xff)<<48 | - ((qemuWord>>16)&0xff)<<40 | - ((qemuWord>>24)&0xff)<<32 | - ((qemuWord>>32)&0xff)<<24 | - ((qemuWord>>40)&0xff)<<16 | - ((qemuWord>>48)&0xff)<<8 | - ((qemuWord>>56)&0xff)<<0); - fwrite(&verilogWord, 8, 1, outFile); - } while(bytesReturned!=0); - return 0; -} diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index 326c397de..6a6ad267a 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -6,7 +6,7 @@ SHELL := /bin/bash .PHONY: profile run questa clean # verilator configurations -OPT= +OPT=--assert PARAMS?=--no-trace-top NONPROF?=--stats VERILATOR_DIR=${WALLY}/sim/verilator diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index f4f7c2b5b..3674303eb 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -46,14 +46,14 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( input logic [P.NE+1:0] FmaSe, // the sum's exponent input logic [P.FMALEN-1:0] FmaSm, // the positive sum input logic FmaASticky, // sticky bit that is calculated during alignment - input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count + input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count //divide signals input logic DivSticky, // divider sticky bit input logic [P.NE+1:0] DivUe, // divsqrt exponent input logic [P.DIVb:0] DivUm, // divsqrt significand // conversion signals input logic CvtCs, // the result's sign - input logic [P.NE:0] CvtCe, // the calculated expoent + input logic [P.NE:0] CvtCe, // the calculated exponent input logic CvtResSubnormUf, // the convert result is subnormal or underflows input logic [P.LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by input logic ToInt, // is fp->int (since it's writting to the integer register) diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv index 37c1e3ac9..dee3d3c99 100644 --- a/src/uncore/spi_controller.sv +++ b/src/uncore/spi_controller.sv @@ -75,7 +75,6 @@ module spi_controller ( logic ShiftEdgePulse; logic SampleEdgePulse; logic EndOfFramePulse; - logic PhaseOneOffset; // Frame stuff logic [3:0] BitNum; @@ -93,6 +92,7 @@ module spi_controller ( logic [7:0] sckcs; logic [7:0] intercs; logic [7:0] interxfr; + logic Phase; logic HasCSSCK; logic HasSCKCS; @@ -109,7 +109,6 @@ module spi_controller ( logic DelayIsNext; logic DelayState; - // Convenient Delay Reg Names assign cssck = Delay0[7:0]; assign sckcs = Delay0[15:8]; @@ -142,6 +141,7 @@ module spi_controller ( assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame; assign EndTransmission = TransmitFIFOEmpty & EndOfFrame; + assign Phase = SckMode[0]; always_ff @(posedge PCLK) begin if (~PRESETn) begin @@ -152,7 +152,7 @@ module spi_controller ( DelayCounter <= 0; end else begin // SCK logic for delay times - if (TransmitStart) begin + if (TransmitStart & ~DelayState) begin SCK <= 0; end else if (SCLKenable) begin SCK <= ~SCK; @@ -161,19 +161,21 @@ module spi_controller ( // Counter for all four delay types if (DelayState & SCK & SCLKenable) begin DelayCounter <= DelayCounter + 8'd1; - end else if (SCLKenable & EndOfDelay) begin + end else if ((SCLKenable & EndOfDelay) | Transmitting) begin DelayCounter <= 8'd0; end // SPICLK Logic - if (TransmitStart) begin + + if (TransmitStart & ~DelayState) begin SPICLK <= SckMode[1]; - end else if (SCLKenable & Transmitting) begin - SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; + end else if (SCLKenable) begin + if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; + else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1]; end // Reset divider - if (SCLKenable | TransmitStart | ResetSCLKenable) begin + if (SCLKenable | (TransmitStart & ~DelayState) | ResetSCLKenable) begin DivCounter <= 12'b0; end else begin DivCounter <= DivCounter + 12'd1; @@ -208,35 +210,18 @@ module spi_controller ( always_ff @(posedge ~PCLK) begin if (~PRESETn | TransmitStart) begin ShiftEdge <= 0; - PhaseOneOffset <= 0; SampleEdge <= 0; EndOfFrame <= 0; - end else begin - PhaseOneOffset <= (PhaseOneOffset == 0) ? Transmitting & SCLKenable : ~EndOfFrame; - case(SckMode) - 2'b00: begin - ShiftEdge <= SPICLK & ShiftEdgePulse; - SampleEdge <= ~SPICLK & SampleEdgePulse; - EndOfFrame <= SPICLK & EndOfFramePulse; - end - 2'b01: begin - ShiftEdge <= ~SPICLK & ShiftEdgePulse & PhaseOneOffset; - SampleEdge <= SPICLK & SampleEdgePulse; - EndOfFrame <= ~SPICLK & EndOfFramePulse; - end - 2'b10: begin + end else if (^SckMode) begin ShiftEdge <= ~SPICLK & ShiftEdgePulse; SampleEdge <= SPICLK & SampleEdgePulse; EndOfFrame <= ~SPICLK & EndOfFramePulse; - end - 2'b11: begin - ShiftEdge <= SPICLK & ShiftEdgePulse & PhaseOneOffset; + end else begin + ShiftEdge <= SPICLK & ShiftEdgePulse; SampleEdge <= ~SPICLK & SampleEdgePulse; EndOfFrame <= SPICLK & EndOfFramePulse; - end - endcase - end - end + end + end // Logic for continuing to transmit through Delay states after end of frame assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR; @@ -263,18 +248,19 @@ module spi_controller ( TRANSMIT: begin // TRANSMIT case -------------------------------- case(CSMode) AUTOMODE: begin - if (EndTransmission) NextState = INACTIVE; - else if (EndOfFrame) NextState = SCKCS; + if (EndTransmission & ~HasSCKCS) NextState = INACTIVE; + else if (EndOfFrame & HasSCKCS) NextState = SCKCS; + else if (EndOfFrame & ~HasSCKCS) NextState = INTERCS; else NextState = TRANSMIT; end HOLDMODE: begin - if (EndTransmission) NextState = HOLD; - else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; + if (EndOfFrame & HasINTERXFR) NextState = INTERXFR; + else if (EndTransmission) NextState = HOLD; else NextState = TRANSMIT; end OFFMODE: begin - if (EndTransmission) NextState = INACTIVE; - else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR; + if (EndOfFrame & HasINTERXFR) NextState = INTERXFR; + else if (EndTransmission) NextState = HOLD; else NextState = TRANSMIT; end default: NextState = TRANSMIT; @@ -282,14 +268,7 @@ module spi_controller ( end SCKCS: begin // SCKCS case -------------------------------------- if (EndOfSCKCS) begin - if (~TransmitRegLoaded) begin - // if (CSMode == AUTOMODE) NextState = INACTIVE; - if (CSMode == HOLDMODE) NextState = HOLD; - else NextState = INACTIVE; - end else begin - if (HasINTERCS) NextState = INTERCS; - else NextState = TRANSMIT; - end + NextState = INTERCS; end else begin NextState = SCKCS; end @@ -303,15 +282,18 @@ module spi_controller ( end INTERCS: begin // INTERCS case ---------------------------------- if (EndOfINTERCS) begin - if (HasCSSCK) NextState = CSSCK; - else NextState = TRANSMIT; + if (TransmitRegLoaded) begin + if (HasCSSCK) NextState = CSSCK; + else NextState = TRANSMIT; + end else NextState = INACTIVE; end else begin NextState = INTERCS; end end INTERXFR: begin // INTERXFR case -------------------------------- if (EndOfINTERXFR) begin - NextState = TRANSMIT; + if (TransmitRegLoaded) NextState = TRANSMIT; + else NextState = HOLD; end else begin NextState = INTERXFR; end diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 63b605679..7e68c28c0 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -28,7 +28,7 @@ all: $(OBJDUMPS) $(MEMFILES) # Assemble into object files %.$(OBJEXT): %.$(AEXT) - riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< + riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval -mabi=lp64 $< # Preprocess assembly files %.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S index fb5cfd436..ef0c283ec 100644 --- a/tests/coverage/csrwrites.S +++ b/tests/coverage/csrwrites.S @@ -38,6 +38,9 @@ main: csrrw t1, menvcfg, t0 csrrw t2, senvcfg, t0 + # Test writing to TIME CSR + csrw time, zero + # testing FIOM with different privilege modes # setting environment config (to both 1 and 0) in each privilege mode csrsi menvcfg, 1 diff --git a/tests/coverage/fround.S b/tests/coverage/fround.S deleted file mode 100644 index 7d469d773..000000000 --- a/tests/coverage/fround.S +++ /dev/null @@ -1,18 +0,0 @@ -// fround.s - -#include "WALLY-init-lib.h" - -# run-elf.bash find this in project description -main: - - bseti t0, zero, 14 # turn on FPU - csrs mstatus, t0 - - # test fround behavior on NaN - li t0, 0x7FC00001 - fmv.w.x ft0, t0 - fround.s ft1, ft0 - j done - -.align 10 -data_start: diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 43e7b6604..285a170cb 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -81,6 +81,7 @@ main: .word 0xFF00302F // illegal Atomic instruction .word 0xFF00402F // illegal Atomic instruction .word 0x00000873 // illegal CSR instruction + .word 0x31bf1f93 // illegal aes64ksli1 instruction # Illegal CMO instructions because envcfg is 0 and system is in user Mode li a0, 0 diff --git a/tests/coverage/ifu.S b/tests/coverage/ifu.S index 72c515287..eaceb71ce 100644 --- a/tests/coverage/ifu.S +++ b/tests/coverage/ifu.S @@ -43,35 +43,23 @@ main: .hword 0x9C41 // line 134 Illegal compressed instruction # Zcb coverage tests - # could restore assembly language versions when GCC supports Zcb mv s0, sp - #c.lbu s1, 0(s0) // exercise c.lbu - .hword 0x8004 // c.lbu s1, 0(s0) - #c.lh s1, 0(s0) // exercise c.lh - .hword 0x8444 // c.lh s1, 0(s0) - #c.lhu s1, 0(s0) // exercise c.lhu - .hword 0x8404 // c.lhu s1, 0(s0) - #c.sb s1, 0(s0) // exercise c.sb - .hword 0x8804 // c.sb s1, 0(s0) - #c.sh s1, 0(s0) // exercise c.sh - .hword 0x8C04 // c.sh s1, 0(s0) + c.lbu s1, 0(s0) // exercise c.lbu + c.lh s1, 0(s0) // exercise c.lh + c.lhu s1, 0(s0) // exercise c.lhu + c.sb s1, 0(s0) // exercise c.sb + c.sh s1, 0(s0) // exercise c.sh .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction li s0, 0xFF - # c.zext.b s0 // exercise c.zext.b - .hword 0x9C61 // c.zext.b s0 - # c.sext.b s0 // exercise c.sext.b - .hword 0x9C65 // c.sext.b s0 - # c.zext.h s0 // exercise c.zext.h - .hword 0x9C69 // c.zext.h s0 - # c.sext.h s0 // exercise c.sext.h - .hword 0x9C6D // c.sext.h s0 - # c.zext.w s0 // exercise c.zext.w - .hword 0x9C71 // c.zext.w s0 - # c.not s0 // exercise c.not - .hword 0x9C75 // c.not s0 + c.zext.b s0 // exercise c.zext.b + c.sext.b s0 // exercise c.sext.b + c.zext.h s0 // exercise c.zext.h + c.sext.h s0 // exercise c.sext.h + c.zext.w s0 // exercise c.zext.w + c.not s0 // exercise c.not .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 1af15add7..d0d3f94f4 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -304,7 +304,7 @@ sretdone: li a0, 3 ecall # exercise sfence.inval.ir instruction - .word 0x18100073 + sfence.inval.ir # exercise sret with rs1 not 0 .word 0x102F8073