Missed some style module declarations

This commit is contained in:
James E. Stine 2024-03-05 09:06:48 -06:00
parent 5e247b9bf3
commit 5aab40a35f
8 changed files with 9 additions and 19 deletions

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@ -25,8 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_sbox(input logic [7:0] in,
output logic [7:0] out);
module aes_inv_sbox(input logic [7:0] in, output logic [7:0] out);
always_comb
begin

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@ -25,8 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_sbox_word(input logic [31:0] in,
output logic [31:0] out);
module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out);
// Declare the SBOX for (least significant) byte 0 of the input
aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));

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@ -25,8 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_inv_shiftrow(input logic [127:0] DataIn,
output logic [127:0] DataOut);
module aes_inv_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96],
DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64],

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@ -26,8 +26,7 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_mixcolumns(input logic [31:0] in,
output logic [31:0] out);
module aes_mixcolumns(input logic [31:0] in, output logic [31:0] out);
logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp;
logic [15:0] rrot8_1, rrot8_2;

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@ -25,8 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_sbox(input logic [7:0] in,
output logic [7:0] out);
module aes_sbox(input logic [7:0] in, output logic [7:0] out);
// case statement to lookup the value in the rijndael table
always_comb

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@ -25,8 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_sbox_word(input logic [31:0] in,
output logic [31:0] out);
module aes_sbox_word(input logic [31:0] in, output logic [31:0] out);
// Declare the SBOX for (least significant) byte 0 of the input
aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));

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@ -25,9 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes_shiftrow
(input logic [127:0] DataIn,
output logic [127:0] DataOut);
module aes_shiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],

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@ -25,9 +25,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module galoismult_forward (
input logic [7:0] in,
output logic [7:0] out);
module galoismult_forward(input logic [7:0] in, output logic [7:0] out);
logic [7:0] leftshift;