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The LSU is properly using FlushW rather than TrapM.

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This commit is contained in:
Ross Thompson 2022-12-22 21:43:25 -06:00
parent ce7e1073fa
commit 5a9e94048a
2 changed files with 2 additions and 2 deletions
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2
pipelined/src/hazard/hazard.sv
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@ -87,7 +87,7 @@ module hazard(
// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));
//assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM; //assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM;
assign StallWCause = (IFUStallF & ~(FlushDCause)) | (LSUStallM & ~TrapM); assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
// Stall each stage for cause or if the next stage is stalled // Stall each stage for cause or if the next stage is stalled
assign #1 StallF = StallFCause | StallD; assign #1 StallF = StallFCause | StallD;

2
pipelined/src/wally/wallypipelinedcore.sv
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@ -247,7 +247,7 @@ module wallypipelinedcore (
lsu lsu( lsu lsu(
.clk, .reset, .StallM, .FlushM, .StallW, .clk, .reset, .StallM, .FlushM, .StallW,
.FlushW(TrapM), .FlushW,
// CPU interface // CPU interface
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
.AtomicM, .AtomicM,