diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..effd553a6 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 7587a9f2c..543b793c0 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -78,6 +78,9 @@ // Address space `define RESET_VECTOR 64'h0000000000001000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index fc63937c1..823165127 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -79,6 +79,9 @@ // Address space `define RESET_VECTOR 64'h0000000000001000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 42e20affe..61977f046 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -80,6 +80,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 022447ff6..8c96f430a 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -78,6 +78,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv32ia/wally-config.vh b/pipelined/config/rv32ia/wally-config.vh index 93042b8c0..4850fe063 100644 --- a/pipelined/config/rv32ia/wally-config.vh +++ b/pipelined/config/rv32ia/wally-config.vh @@ -80,6 +80,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index fcd3c8e5e..0faed8fcc 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -78,6 +78,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 005a1de3f..952741763 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -59,7 +59,7 @@ // TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 +`define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index d25827b73..b72405b58 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -84,6 +84,9 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 6af3c7bd9..622cfd5da 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv64ia/wally-config.vh b/pipelined/config/rv64ia/wally-config.vh index 43bd1ecd4..84289de91 100644 --- a/pipelined/config/rv64ia/wally-config.vh +++ b/pipelined/config/rv64ia/wally-config.vh @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index c46dbfe70..1c320268b 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index cd1dbd772..6891c7d6c 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -52,14 +52,14 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { #vsim -coverage -lib work_$2 workopt_$2 # power add generates the logging necessary for saif generation. - power add -r /dut/core/* + # power add -r /dut/core/* run -all - power off -r /dut/core/* + # power off -r /dut/core/* } #coverage report -file wally-pipelined-coverage.txt # These aren't doing anything helpful #coverage report -memory #profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 -power report -all -bsaif power.saif +#power report -all -bsaif power.saif quit diff --git a/pipelined/regression/wkdir/README b/pipelined/regression/wkdir/README deleted file mode 100644 index e69de29bb..000000000 diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv index e93822ee5..fb8e1ad9a 100644 --- a/pipelined/src/fpu/fcvtfp.sv +++ b/pipelined/src/fpu/fcvtfp.sv @@ -30,11 +30,17 @@ module cvtfp ( logic [31:0] DSRes; // double to single precision result + // add support for all formats + // consider reordering code blocks so upconverting is in one region of the file + // and downconverting is in the other region. /////////////////////////////////////////////////////////////////////////////// - // LZC + // LZC: Leading Zero Counter /////////////////////////////////////////////////////////////////////////////// + // *** consider sharing this with fcvtint + // *** emphasize parallel structure between the two + // *** add a priorityencoder module to generic (similar to priorityonehot) and use it // LZC - find the first 1 in the input's mantissa logic [8:0] i,NormCnt; diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv index d394d7c3e..6a6686993 100644 --- a/pipelined/src/fpu/fcvtint.sv +++ b/pipelined/src/fpu/fcvtint.sv @@ -61,6 +61,10 @@ module fcvt ( // fcvt.d.l = 100 // fcvt.d.lu = 110 // {long, unsigned, to int} + + // *** revisit this module, explain in more depth + // should the int to fp and fp to int paths be separated? + // add support for all formats // calculate signals based off the input and output's size assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]); diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 50100c3c7..c5184c578 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; logic Carry, Neg; logic LT, LTU; - logic Overflow; logic W64, SubArith, ALUOp; logic [2:0] ALUFunct; + logic Asign, Bsign; // Extract control signals // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word @@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) ( // Shifts shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); - // condition code flags based on subtract output + // condition code flags based on subtract output Sum = A-B // Overflow occurs when the numbers being subtracted have the opposite sign // and the result has the opposite sign of A - assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]); assign Neg = Sum[WIDTH-1]; - assign LT = Neg ^ Overflow; + assign Asign = A[WIDTH-1]; + assign Bsign = B[WIDTH-1]; + assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow assign LTU = ~Carry; // SLT diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 25e929a21..1f7ae6b11 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -33,7 +33,8 @@ module privdec ( input logic [31:20] InstrM, - input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, TrappedSRETM, + input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, + input logic TrappedSRETM, WFITimeoutM, input logic [1:0] PrivilegeModeW, input logic STATUS_TSR, output logic IllegalInstrFaultM, @@ -51,7 +52,6 @@ module privdec ( assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); // *** & (PrivilegedModeW == `M_MODE | ~STATUS_TVM); // *** does this work in U mode? assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); - assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions - - // *** initially, wfi is nop + assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | + TrappedSRETM | WFITimeoutM; // *** generalize this for other instructions endmodule diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 003a84b76..c60f338e6 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -104,6 +104,7 @@ module privileged ( logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; logic md; logic StallMQ; + logic WFITimeoutM; /////////////////////////////////////////// @@ -114,24 +115,6 @@ module privileged ( assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // PrivilegeMode FSM -/* -----\/----- EXCLUDED -----\/----- - always_comb begin - TrappedSRETM = 0; - if (mretM) NextPrivilegeModeM = STATUS_MPP; - else if (sretM) - if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin - TrappedSRETM = 1; - NextPrivilegeModeM = PrivilegeModeW; - end else NextPrivilegeModeM = {1'b0, STATUS_SPP}; - else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) - if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) - NextPrivilegeModeM = `S_MODE; - else NextPrivilegeModeM = `M_MODE; - end else NextPrivilegeModeM = PrivilegeModeW; - end - - -----/\----- EXCLUDED -----/\----- */ - always_comb begin if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) @@ -149,14 +132,21 @@ module privileged ( flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); - // *** WFI could be implemented here and depends on TW + /////////////////////////////////////////// + // WFI timeout Privileged Spec 3.1.6.5 + /////////////////////////////////////////// + if (`U_SUPPORTED) begin + logic [`WFI_TIMEOUT_BIT:0] WFICount; + floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICount+1, WFICount); // count while in WFI + assign WFITimeoutM = STATUS_TW & PrivilegeModeW != `M_MODE & WFICount[`WFI_TIMEOUT_BIT]; + end else assign WFITimeoutM = 0; /////////////////////////////////////////// // decode privileged instructions /////////////////////////////////////////// privdec pmd(.InstrM(InstrM[31:20]), - .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, + .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM, .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); @@ -233,7 +223,7 @@ module privileged ( .PCM, .InstrMisalignedAdrM, .IEUAdrM, .InstrM, - .InstrValidM, .CommittedM, .DivE, + .InstrValidM, .CommittedM, .DivE, .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .InterruptM, .ExceptionM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index a2cc6ef35..1cc21579b 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -46,7 +46,7 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM, input logic [31:0] InstrM, - input logic InstrValidM, CommittedM, DivE, + input logic InstrValidM, CommittedM, DivE, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic ExceptionM,