diff --git a/src/ifu/fetchbuffer.sv b/src/ifu/fetchbuffer.sv
index d532aa51f..2efd2a6c0 100644
--- a/src/ifu/fetchbuffer.sv
+++ b/src/ifu/fetchbuffer.sv
@@ -47,19 +47,6 @@ module fetchbuffer import cvw::*; #(parameter cvw_t P) (
   flopenl #(32) f1 (.clk, .load(reset | FlushD), .en(WritePtr[1]), .d(WriteData), .val(nop), .q(Readf1));
   flopenl #(32) f2 (.clk, .load(reset | FlushD), .en(WritePtr[2]), .d(WriteData), .val(nop), .q(Readf2));
 
-  // always_comb begin : readMuxes
-  //   // Mux read data from the three registers
-  //   case (ReadPtr)
-  //     3'b001:  ReadFetchBuffer = Readf0;
-  //     3'b010:  ReadFetchBuffer = Readf1;
-  //     3'b100:  ReadFetchBuffer = Readf2;
-  //     default: ReadFetchBuffer = nop; // just in case?
-  //   endcase
-  //   // issue nop when appropriate
-  //   ReadData = Empty ? nop : ReadFetchBuffer;
-  // end
-
-
   // Fetch buffer entries anded with read ptr for AO Muxing
   logic [31:0] DaoArr [2:0];
   //     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Make parameterizable
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 43de35c5f..e91f9123b 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -304,8 +304,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   assign GatedStallD = StallD & ~SelSpillNextF;
 
   // flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
-  // TODO: Test this?!?!?!
-  fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF); // Figure out what TODO with StallF
+  fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF);
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // PCNextF logic