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add flopenrs back
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52
src/generic/flop/flopenrs.sv
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52
src/generic/flop/flopenrs.sv
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///////////////////////////////////////////
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// flopenrs.sv
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//
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// Written: matthew.n.otto@okstate.edu 15 April 2024
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// Modified:
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//
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// Purpose: Scannable D flip-flop with enable, synchronous reset
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License Version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module flopenrs #(parameter WIDTH = 8) (
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input logic clk, reset, en,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q,
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input logic scan, // scan enable
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input logic scanin,
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output logic scanout
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);
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logic [WIDTH-1:0] dmux;
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assign dmux[WIDTH-1] = scan ? scanin : d[WIDTH-1];
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assign scanout = q[0];
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genvar i;
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for (i=0; i<WIDTH-1; i=i+1) begin
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assign dmux[i] = scan ? q[i+1] : d[i];
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end
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always_ff @(posedge clk)
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if (reset)
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q <= '0;
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else if (en || scan)
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q <= dmux;
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endmodule
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