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Merge pull request #420 from ross144/main

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Fixed Imperas Linux testbench
This commit is contained in:
David Harris 2023-10-05 09:34:04 -07:00 committed by GitHub
commit 59f9345db9
2 changed files with 76 additions and 71 deletions
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10
testbench/common/wallyTracer.sv
View File

@ -40,7 +40,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic StallF, StallD; logic StallF, StallD;
logic STATUS_SXL, STATUS_UXL; logic STATUS_SXL, STATUS_UXL;
logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
logic [P.XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
logic InstrValidM, InstrValidW; logic InstrValidM, InstrValidW;
logic StallE, StallM, StallW; logic StallE, StallM, StallW;
logic FlushD, FlushE, FlushM, FlushW; logic FlushD, FlushE, FlushM, FlushW;
@ -259,10 +259,10 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM; assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
// pipeline to writeback stage // pipeline to writeback stage
flopenrc #(P.XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE); flopenrc #(32) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
flopenrc #(P.XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM); flopenrc #(32) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
flopenrc #(P.XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW); flopenrc #(32) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
flopenrc #(P.XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW); flopenrc #(32) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW); flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW); flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW); flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);

137
testbench/testbench-linux-imperas.sv
View File

@ -24,7 +24,8 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" `include "config.vh"
`include "BranchPredictorType.vh"
// This is set from the command line script // This is set from the command line script
// `define USE_IMPERAS_DV // `define USE_IMPERAS_DV
@ -33,6 +34,8 @@
`include "idv/idv.svh" `include "idv/idv.svh"
`endif `endif
import cvw::*;
`define DEBUG_TRACE 0 `define DEBUG_TRACE 0
// Debug Levels // Debug Levels
// 0: don't check against QEMU // 0: don't check against QEMU
@ -61,8 +64,7 @@ module testbench;
`endif `endif
`include "parameter-defs.vh"
@ -96,40 +98,40 @@ module testbench;
integer TokenIndex``STAGE; \ integer TokenIndex``STAGE; \
integer MarkerIndex``STAGE; \ integer MarkerIndex``STAGE; \
integer NumCSR``STAGE; \ integer NumCSR``STAGE; \
logic [`XLEN-1:0] ExpectedPC``STAGE; \ logic [P.XLEN-1:0] ExpectedPC``STAGE; \
logic [31:0] ExpectedInstr``STAGE; \ logic [31:0] ExpectedInstr``STAGE; \
string text``STAGE; \ string text``STAGE; \
string MemOp``STAGE; \ string MemOp``STAGE; \
string RegWrite``STAGE; \ string RegWrite``STAGE; \
integer ExpectedRegAdr``STAGE; \ integer ExpectedRegAdr``STAGE; \
logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ logic [P.XLEN-1:0] ExpectedRegValue``STAGE; \
logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ logic [P.XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
string ExpectedCSRArray``STAGE[10:0]; \ string ExpectedCSRArray``STAGE[10:0]; \
logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? logic [P.XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
`DECLARE_TRACE_SCANNER_SIGNALS(E) `DECLARE_TRACE_SCANNER_SIGNALS(E)
`DECLARE_TRACE_SCANNER_SIGNALS(M) `DECLARE_TRACE_SCANNER_SIGNALS(M)
// M-stage expected values // M-stage expected values
logic checkInstrM; logic checkInstrM;
integer MIPexpected, SIPexpected; integer MIPexpected, SIPexpected;
string name; string name;
logic [`AHBW-1:0] readDataExpected; logic [P.AHBW-1:0] readDataExpected;
// W-stage expected values // W-stage expected values
logic checkInstrW; logic checkInstrW;
logic [`XLEN-1:0] ExpectedPCW; logic [P.XLEN-1:0] ExpectedPCW;
logic [31:0] ExpectedInstrW; logic [31:0] ExpectedInstrW;
string textW; string textW;
string RegWriteW; string RegWriteW;
integer ExpectedRegAdrW; integer ExpectedRegAdrW;
logic [`XLEN-1:0] ExpectedRegValueW; logic [P.XLEN-1:0] ExpectedRegValueW;
string MemOpW; string MemOpW;
logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW; logic [P.XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
integer NumCSRW; integer NumCSRW;
string ExpectedCSRArrayW[10:0]; string ExpectedCSRArrayW[10:0];
logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0]; logic [P.XLEN-1:0] ExpectedCSRArrayValueW[10:0];
logic [`XLEN-1:0] ExpectedIntType; logic [P.XLEN-1:0] ExpectedIntType;
integer NumCSRWIndex; integer NumCSRWIndex;
integer NumCSRPostWIndex; integer NumCSRPostWIndex;
logic [`XLEN-1:0] InstrCountW; logic [P.XLEN-1:0] InstrCountW;
// ========== Interrupt parsing & spoofing ========== // ========== Interrupt parsing & spoofing ==========
string interrupt; string interrupt;
string interruptLine; string interruptLine;
@ -143,7 +145,7 @@ module testbench;
string interruptDesc; string interruptDesc;
integer NextMIPexpected, NextSIPexpected; integer NextMIPexpected, NextSIPexpected;
integer NextMepcExpected; integer NextMepcExpected;
logic [`XLEN-1:0] AttemptedInstructionCount; logic [P.XLEN-1:0] AttemptedInstructionCount;
// ========== Misc Aliases ========== // ========== Misc Aliases ==========
`define RF dut.core.ieu.dp.regf.rf `define RF dut.core.ieu.dp.regf.rf
`define PC dut.core.ifu.pcreg.q `define PC dut.core.ifu.pcreg.q
@ -168,7 +170,7 @@ module testbench;
`define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q `define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q
`define MTVEC `CSR_BASE.csrm.MTVECreg.q `define MTVEC `CSR_BASE.csrm.MTVECreg.q
`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q `define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q `define SATP `CSR_BASE.csrs.csrs.genblk2.SATPreg.q
`define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2] `define INSTRET `CSR_BASE.counters.counters.HPMCOUNTER_REGW[2]
`define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW `define MSTATUS `CSR_BASE.csrsr.MSTATUS_REGW
`define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW `define SSTATUS `CSR_BASE.csrsr.SSTATUS_REGW
@ -249,14 +251,14 @@ module testbench;
initial begin reset_ext <= 1; # 22; reset_ext <= 0; end initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
always begin clk <= 1; # 5; clk <= 0; # 5; end always begin clk <= 1; # 5; clk <= 0; # 5; end
// Wally Interface // Wally Interface
logic [`AHBW-1:0] HRDATAEXT; logic [P.AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT; logic HREADYEXT, HRESPEXT;
logic HCLK, HRESETn; logic HCLK, HRESETn;
logic HREADY; logic HREADY;
logic HSELEXT; logic HSELEXT;
logic [`PA_BITS-1:0] HADDR; logic [P.PA_BITS-1:0] HADDR;
logic [`AHBW-1:0] HWDATA; logic [P.AHBW-1:0] HWDATA;
logic [`XLEN/8-1:0] HWSTRB; logic [P.XLEN/8-1:0] HWSTRB;
logic HWRITE; logic HWRITE;
logic [2:0] HSIZE; logic [2:0] HSIZE;
logic [2:0] HBURST; logic [2:0] HBURST;
@ -273,10 +275,13 @@ module testbench;
logic SDCCmdOut; logic SDCCmdOut;
logic SDCCmdOE; logic SDCCmdOE;
logic [3:0] SDCDatIn; logic [3:0] SDCDatIn;
logic SDCIntr;
// Hardwire UART, GPIO pins // Hardwire UART, GPIO pins
assign GPIOPinsIn = 0; assign GPIOIN = 0;
assign UARTSin = 1; assign UARTSin = 1;
assign SDCIntr = 0;
@ -284,8 +289,8 @@ module testbench;
logic DCacheFlushDone, DCacheFlushStart; logic DCacheFlushDone, DCacheFlushStart;
rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi(); rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
wallyTracer wallyTracer(rvvi); wallyTracer #(P) wallyTracer(rvvi);
trace2log idv_trace2log(rvvi); trace2log idv_trace2log(rvvi);
// trace2cov idv_trace2cov(rvvi); // trace2cov idv_trace2cov(rvvi);
@ -344,23 +349,23 @@ module testbench;
// Privileges for PMA are set in the imperas.ic // Privileges for PMA are set in the imperas.ic
// volatile (IO) regions are defined here // volatile (IO) regions are defined here
// only real ROM/RAM areas are BOOTROM and UNCORE_RAM // only real ROM/RAM areas are BOOTROM and UNCORE_RAM
if (`CLINT_SUPPORTED) begin if (P.CLINT_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE))); void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
end end
if (`GPIO_SUPPORTED) begin if (P.GPIO_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE))); void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
end end
if (`UART_SUPPORTED) begin if (P.UART_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
end end
if (`PLIC_SUPPORTED) begin if (P.PLIC_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE))); void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
end end
if (`SDC_SUPPORTED) begin if (P.SDC_SUPPORTED) begin
void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE))); void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
end end
if(`XLEN==32) begin if(P.XLEN==32) begin
void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH
void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH
void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH
@ -427,28 +432,28 @@ module testbench;
// Wally // Wally
wallypipelinedsoc dut(.clk, .reset, .reset_ext, wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
.HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK,
.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HTRANS, .HMASTLOCK,
.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN, .TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .UARTSin, .UARTSout,
.SDCCLK, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn); .SDCIntr);
// W-stage hardware not needed by Wally itself // W-stage hardware not needed by Wally itself
parameter nop = 'h13; parameter nop = 'h13;
logic [`XLEN-1:0] PCW; logic [P.XLEN-1:0] PCW;
logic [31:0] InstrW; logic [31:0] InstrW;
logic InstrValidW; logic InstrValidW;
logic [`XLEN-1:0] IEUAdrW, WriteDataW; logic [P.XLEN-1:0] IEUAdrW, WriteDataW;
logic TrapW; logic TrapW;
`define FLUSHW dut.core.FlushW `define FLUSHW dut.core.FlushW
`define STALLW dut.core.StallW `define STALLW dut.core.StallW
flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW); flopenrc #(P.XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, `PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW); flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW); flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW); flopenrc #(P.XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW); flopenrc #(P.XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);
flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW); flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
@ -524,29 +529,29 @@ module testbench;
end end
genvar i; genvar i;
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1); `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [P.XLEN-1:0],31,1);
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0); `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [P.XLEN-1:0],P.COUNTERS-1,0);
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(PC, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [P.XLEN-1:0]);
if(!NO_SPOOFING) begin if(!NO_SPOOFING) begin
`INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIE, [11:0]);
`INIT_CHECKPOINT_VAL(MIP, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]);
end end
`INIT_CHECKPOINT_VAL(MCAUSE, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MCAUSE, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SCAUSE, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SCAUSE, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEPC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEPC, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SEPC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SEPC, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]); `INIT_CHECKPOINT_VAL(MCOUNTEREN, [31:0]);
`INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]); `INIT_CHECKPOINT_VAL(SCOUNTEREN, [31:0]);
`INIT_CHECKPOINT_VAL(MSCRATCH, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MSCRATCH, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SSCRATCH, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SSCRATCH, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MTVEC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MTVEC, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(STVEC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(STVEC, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(SATP, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(SATP, [P.XLEN-1:0]);
`INIT_CHECKPOINT_VAL(PRIV, [1:0]); `INIT_CHECKPOINT_VAL(PRIV, [1:0]);
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1); `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_INT_PRIORITY, [2:0],P.PLIC_NUM_SRC,1);
`MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:0],1,0); `MAKE_CHECKPOINT_INIT_SIGNAL(PLIC_INT_ENABLE, [P.PLIC_NUM_SRC:0],1,0);
`INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0); `INIT_CHECKPOINT_PACKED_ARRAY(PLIC_THRESHOLD, [2:0],1,0);
// UART checkpointing does not cover entire UART state // UART checkpointing does not cover entire UART state
// Many UART registers are difficult to initialize because under the hood // Many UART registers are difficult to initialize because under the hood
@ -561,8 +566,8 @@ module testbench;
`INIT_CHECKPOINT_VAL(UART_SCR, [7:0]); `INIT_CHECKPOINT_VAL(UART_SCR, [7:0]);
// xSTATUS need to be handled manually because the most upstream signals // xSTATUS need to be handled manually because the most upstream signals
// are made of individual bits, not registers // are made of individual bits, not registers
`MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0); `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [P.XLEN-1:0],0,0);
`MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0); `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [P.XLEN-1:0],0,0);
// ========== INITIALIZATION ========== // ========== INITIALIZATION ==========
initial begin initial begin
@ -618,7 +623,7 @@ module testbench;
force {`STATUS_SPIE} = initMSTATUS[0][5]; force {`STATUS_SPIE} = initMSTATUS[0][5];
force {`STATUS_MIE} = initMSTATUS[0][3]; force {`STATUS_MIE} = initMSTATUS[0][3];
force {`STATUS_SIE} = initMSTATUS[0][1]; force {`STATUS_SIE} = initMSTATUS[0][1];
force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][P.PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][P.PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
force `INSTRET = CHECKPOINT; force `INSTRET = CHECKPOINT;
while (reset!==1) #1; while (reset!==1) #1;
while (reset!==0) #1; while (reset!==0) #1;
@ -871,7 +876,7 @@ module testbench;
"scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW) "scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
"stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW) "stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
"senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) // "senvcfg": `checkCSR(`CSR_BASE.csrs.SENVCFG_REGW) // *** fix me
"mip": begin "mip": begin
`checkCSR(`CSR_BASE.csrm.MIP_REGW) `checkCSR(`CSR_BASE.csrm.MIP_REGW)
if(!NO_SPOOFING) begin if(!NO_SPOOFING) begin
@ -951,7 +956,7 @@ module testbench;
//////////////////////////////// Extra Features /////////////////////////////// //////////////////////////////// Extra Features ///////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// Function Tracking // Function Tracking
FunctionName FunctionName(.reset(reset), FunctionName #(P) FunctionName(.reset(reset),
.clk(clk), .clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile), .ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile)); .ProgramLabelMapFile(ProgramLabelMapFile));
@ -976,12 +981,12 @@ module testbench;
* explanation of the below algorithm. * explanation of the below algorithm.
*/ */
logic SvMode, PTE_R, PTE_X; logic SvMode, PTE_R, PTE_X;
logic [`XLEN-1:0] SATP, PTE; logic [P.XLEN-1:0] SATP, PTE;
logic [55:0] BaseAdr, PAdr; logic [55:0] BaseAdr, PAdr;
logic [8:0] VPN [2:0]; logic [8:0] VPN [2:0];
logic [11:0] Offset; logic [11:0] Offset;
function logic [`XLEN-1:0] adrTranslator( function logic [P.XLEN-1:0] adrTranslator(
input logic [`XLEN-1:0] adrIn); input logic [P.XLEN-1:0] adrIn);
begin begin
int i; int i;
// Grab the SATP register from privileged unit // Grab the SATP register from privileged unit
@ -995,7 +1000,7 @@ module testbench;
SvMode = SATP[63]; SvMode = SATP[63];
// Only perform translation if translation is on and the processor is not // Only perform translation if translation is on and the processor is not
// in machine mode // in machine mode
if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin
BaseAdr = SATP[43:0] << 12; BaseAdr = SATP[43:0] << 12;
for (i = 2; i >= 0; i--) begin for (i = 2; i >= 0; i--) begin
PAdr = BaseAdr + (VPN[i] << 3); PAdr = BaseAdr + (VPN[i] << 3);