mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
59a2c09c5e
34
linux/testvector-generation/genRecording.sh
Executable file
34
linux/testvector-generation/genRecording.sh
Executable file
@ -0,0 +1,34 @@
|
|||||||
|
#!/bin/bash
|
||||||
|
imageDir=$RISCV/buildroot/output/images
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||||||
|
tvDir=$RISCV/linux-testvectors
|
||||||
|
recordFile="$tvDir/all.qemu"
|
||||||
|
|
||||||
|
read -p "Warning: running this script will overwrite $recordFile
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||||||
|
Would you like to proceed? (y/n) " -n 1 -r
|
||||||
|
echo
|
||||||
|
if [[ $REPLY =~ ^[Yy]$ ]]
|
||||||
|
then
|
||||||
|
# Create Output Directory
|
||||||
|
echo "Elevating permissions to create $recordFile"
|
||||||
|
sudo mkdir -p $tvDir
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||||||
|
sudo chown cad $tvDir
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||||||
|
sudo touch $recordFile
|
||||||
|
sudo chmod a+rw $recordFile
|
||||||
|
|
||||||
|
# Compile Devicetree from Source
|
||||||
|
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb
|
||||||
|
|
||||||
|
# QEMU Simulation
|
||||||
|
echo "Launching QEMU!"
|
||||||
|
qemu-system-riscv64 \
|
||||||
|
-M virt -dtb ../devicetree/wally-virt.dtb \
|
||||||
|
-nographic \
|
||||||
|
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
|
||||||
|
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile
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||||||
|
|
||||||
|
# Cleanup
|
||||||
|
echo "Elevating permissions to restrict write access to $recordFile"
|
||||||
|
sudo chown cad $recordFile
|
||||||
|
sudo chmod o-w $recordFile
|
||||||
|
fi
|
||||||
|
|
||||||
@ -1,25 +0,0 @@
|
|||||||
define genTrace
|
|
||||||
# Arguments
|
|
||||||
set $tcpPort=$arg0
|
|
||||||
set $vmlinux=$arg1
|
|
||||||
|
|
||||||
# GDB config
|
|
||||||
set pagination off
|
|
||||||
set logging overwrite on
|
|
||||||
set logging redirect on
|
|
||||||
set confirm off
|
|
||||||
|
|
||||||
# Connect to QEMU session
|
|
||||||
eval "target extended-remote :%d",$tcpPort
|
|
||||||
|
|
||||||
# Symbol Files
|
|
||||||
eval "file %s",$vmlinux
|
|
||||||
|
|
||||||
# Run until Linux login prompt
|
|
||||||
b do_idle
|
|
||||||
ignore 1 2
|
|
||||||
c
|
|
||||||
|
|
||||||
kill
|
|
||||||
q
|
|
||||||
end
|
|
||||||
@ -1,13 +1,12 @@
|
|||||||
#!/bin/bash
|
#!/bin/bash
|
||||||
tcpPort=1234
|
tcpPort=1234
|
||||||
imageDir=$RISCV/buildroot/output/images
|
imageDir=$RISCV/buildroot/output/images
|
||||||
outDir=$RISCV/linux-testvectors
|
tvDir=$RISCV/linux-testvectors
|
||||||
recordFile="$outDir/all.qemu"
|
recordFile="$tvDir/all.qemu"
|
||||||
traceFile="$outDir/all.txt"
|
traceFile="$tvDir/all.txt"
|
||||||
interruptsFile="$outDir/interrupts.txt"
|
interruptsFile="$tvDir/interrupts.txt"
|
||||||
|
|
||||||
read -p "Warning: running this script will overwrite the contents of:
|
read -p "Warning: running this script will overwrite the contents of:
|
||||||
* $recordFile
|
|
||||||
* $traceFile
|
* $traceFile
|
||||||
* $interruptsFile
|
* $interruptsFile
|
||||||
Would you like to proceed? (y/n) " -n 1 -r
|
Would you like to proceed? (y/n) " -n 1 -r
|
||||||
@ -15,12 +14,11 @@ echo
|
|||||||
if [[ $REPLY =~ ^[Yy]$ ]]
|
if [[ $REPLY =~ ^[Yy]$ ]]
|
||||||
then
|
then
|
||||||
# Create Output Directory
|
# Create Output Directory
|
||||||
sudo mkdir -p $outDir
|
echo "Elevating permissions to create $traceFile, $interruptsFile"
|
||||||
sudo chown cad $outDir
|
sudo mkdir -p $tvDir
|
||||||
sudo touch $recordFile
|
sudo chown cad $tvDir
|
||||||
sudo touch $traceFile
|
sudo touch $traceFile
|
||||||
sudo touch $interruptsFile
|
sudo touch $interruptsFile
|
||||||
sudo chmod a+rw $recordFile
|
|
||||||
sudo chmod a+rw $traceFile
|
sudo chmod a+rw $traceFile
|
||||||
sudo chmod a+rw $interruptsFile
|
sudo chmod a+rw $interruptsFile
|
||||||
|
|
||||||
@ -28,21 +26,19 @@ then
|
|||||||
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb
|
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb
|
||||||
|
|
||||||
# QEMU Simulation
|
# QEMU Simulation
|
||||||
|
echo "Launching QEMU in replay mode!"
|
||||||
(qemu-system-riscv64 \
|
(qemu-system-riscv64 \
|
||||||
-M virt -dtb ../devicetree/wally-virt.dtb \
|
-M virt -dtb ../devicetree/wally-virt.dtb \
|
||||||
-nographic -serial /dev/null \
|
-nographic \
|
||||||
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
|
-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
|
||||||
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \
|
-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=replay,rrfile=$recordFile \
|
||||||
-d nochain,cpu,in_asm,int \
|
-d nochain,cpu,in_asm,int \
|
||||||
-gdb tcp::$tcpPort -S \
|
2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile)
|
||||||
2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) \
|
|
||||||
& riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\""
|
|
||||||
|
|
||||||
# Cleanup
|
# Cleanup
|
||||||
sudo chown cad $recordFile
|
echo "Elevating permissions to restrict write access to $traceFile, $interruptsFile"
|
||||||
sudo chown cad $traceFile
|
sudo chown cad $traceFile
|
||||||
sudo chown cad $interruptsFile
|
sudo chown cad $interruptsFile
|
||||||
sudo chmod o-w $recordFile
|
|
||||||
sudo chmod o-w $traceFile
|
sudo chmod o-w $traceFile
|
||||||
sudo chmod o-w $interruptsFile
|
sudo chmod o-w $interruptsFile
|
||||||
fi
|
fi
|
||||||
|
|||||||
@ -117,7 +117,7 @@
|
|||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 53
|
`define PLIC_NUM_SRC 53
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt"
|
||||||
|
|||||||
@ -123,7 +123,7 @@
|
|||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 53
|
`define PLIC_NUM_SRC 53
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
|
||||||
|
|||||||
@ -117,11 +117,11 @@
|
|||||||
`define UART_PRESCALE 1
|
`define UART_PRESCALE 1
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 4
|
`define PLIC_NUM_SRC 10
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
`define PLIC_NUM_SRC_LT_32
|
`define PLIC_NUM_SRC_LT_32
|
||||||
`define PLIC_GPIO_ID 3
|
`define PLIC_GPIO_ID 3
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
||||||
|
|||||||
@ -115,11 +115,11 @@
|
|||||||
`define UART_PRESCALE 1
|
`define UART_PRESCALE 1
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 4
|
`define PLIC_NUM_SRC 10
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
`define PLIC_NUM_SRC_LT_32
|
`define PLIC_NUM_SRC_LT_32
|
||||||
`define PLIC_GPIO_ID 3
|
`define PLIC_GPIO_ID 3
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
||||||
|
|||||||
@ -115,11 +115,11 @@
|
|||||||
`define UART_PRESCALE 1
|
`define UART_PRESCALE 1
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 4
|
`define PLIC_NUM_SRC 10
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
`define PLIC_NUM_SRC_LT_32
|
`define PLIC_NUM_SRC_LT_32
|
||||||
`define PLIC_GPIO_ID 3
|
`define PLIC_GPIO_ID 3
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt"
|
||||||
|
|||||||
@ -117,11 +117,11 @@
|
|||||||
`define UART_PRESCALE 1
|
`define UART_PRESCALE 1
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 4
|
`define PLIC_NUM_SRC 10
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
`define PLIC_NUM_SRC_LT_32
|
`define PLIC_NUM_SRC_LT_32
|
||||||
`define PLIC_GPIO_ID 3
|
`define PLIC_GPIO_ID 3
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt"
|
||||||
|
|||||||
@ -118,11 +118,11 @@
|
|||||||
`define UART_PRESCALE 1
|
`define UART_PRESCALE 1
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 4
|
`define PLIC_NUM_SRC 10
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
`define PLIC_NUM_SRC_LT_32
|
`define PLIC_NUM_SRC_LT_32
|
||||||
`define PLIC_GPIO_ID 3
|
`define PLIC_GPIO_ID 3
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
||||||
|
|||||||
@ -118,11 +118,11 @@
|
|||||||
`define UART_PRESCALE 1
|
`define UART_PRESCALE 1
|
||||||
|
|
||||||
// Interrupt configuration
|
// Interrupt configuration
|
||||||
`define PLIC_NUM_SRC 4
|
`define PLIC_NUM_SRC 10
|
||||||
// comment out the following if >=32 sources
|
// comment out the following if >=32 sources
|
||||||
`define PLIC_NUM_SRC_LT_32
|
`define PLIC_NUM_SRC_LT_32
|
||||||
`define PLIC_GPIO_ID 3
|
`define PLIC_GPIO_ID 3
|
||||||
`define PLIC_UART_ID 4
|
`define PLIC_UART_ID 10
|
||||||
|
|
||||||
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
|
||||||
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
|
||||||
|
|||||||
@ -5,39 +5,39 @@ add wave -noupdate /testbench/reset
|
|||||||
add wave -noupdate /testbench/reset_ext
|
add wave -noupdate /testbench/reset_ext
|
||||||
add wave -noupdate /testbench/memfilename
|
add wave -noupdate /testbench/memfilename
|
||||||
add wave -noupdate /testbench/dut/core/SATP_REGW
|
add wave -noupdate /testbench/dut/core/SATP_REGW
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
|
||||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM
|
add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
|
||||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
|
||||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
||||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
||||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
|
||||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||||
@ -51,15 +51,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
|
|||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
|
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
|
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
|
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
|
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
|
add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
add wave -noupdate -group {Memory Stage} /testbench/InstrMName
|
||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||||
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||||
@ -175,186 +175,186 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK
|
|||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
|
||||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
|
||||||
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
|
add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
|
add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
|
||||||
add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
|
add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
|
||||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
|
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
|
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
|
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF
|
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM
|
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
||||||
@ -368,6 +368,19 @@ add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
|||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
||||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingArray
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingMaxP
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingPGrouped
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingRequestsAtMaxP
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests
|
||||||
|
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
||||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
||||||
@ -396,35 +409,44 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
|||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART
|
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN
|
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb
|
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb
|
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb
|
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb
|
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/Din
|
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR
|
||||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/LCR
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata
|
||||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN
|
||||||
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb
|
||||||
|
add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
||||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
||||||
@ -474,8 +496,8 @@ add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/Nex
|
|||||||
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWWrite
|
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWWrite
|
||||||
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE
|
add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 7} {283655 ns} 1} {{Cursor 5} {86805 ns} 0} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1}
|
WaveRestoreCursors {{Cursor 5} {0 ns} 0}
|
||||||
quietly wave cursor active 2
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 314
|
configure wave -valuecolwidth 314
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -490,4 +512,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {86757 ns} {87017 ns}
|
WaveRestoreZoom {0 ns} {224 ns}
|
||||||
|
|||||||
@ -113,7 +113,7 @@ module plic (
|
|||||||
24'h002004: intEn[N:32] <= #1 Din[31:0];
|
24'h002004: intEn[N:32] <= #1 Din[31:0];
|
||||||
`endif
|
`endif
|
||||||
24'h200000: intThreshold[2:0] <= #1 Din[2:0];
|
24'h200000: intThreshold[2:0] <= #1 Din[2:0];
|
||||||
24'h200004: intInProgress <= #1 intInProgress & ~(4'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
|
24'h200004: intInProgress <= #1 intInProgress & ~(`PLIC_NUM_SRC'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
|
||||||
endcase
|
endcase
|
||||||
// reading
|
// reading
|
||||||
if (memread)
|
if (memread)
|
||||||
@ -132,7 +132,7 @@ module plic (
|
|||||||
24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]};
|
24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]};
|
||||||
24'h200004: begin
|
24'h200004: begin
|
||||||
Dout <= #1 {26'b0,intClaim};
|
Dout <= #1 {26'b0,intClaim};
|
||||||
intInProgress <= #1 intInProgress | (4'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
|
intInProgress <= #1 intInProgress | (`PLIC_NUM_SRC'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
|
||||||
end
|
end
|
||||||
default: Dout <= #1 32'h0; // invalid access
|
default: Dout <= #1 32'h0; // invalid access
|
||||||
endcase
|
endcase
|
||||||
@ -155,7 +155,7 @@ module plic (
|
|||||||
// pending updates
|
// pending updates
|
||||||
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
|
// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
|
||||||
assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress
|
assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress
|
||||||
~({4{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
|
~({N{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
|
||||||
flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
|
flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
|
||||||
|
|
||||||
// pending array - indexed by priority_lvl x source_ID
|
// pending array - indexed by priority_lvl x source_ID
|
||||||
|
|||||||
@ -278,12 +278,12 @@ module uartPC16550D(
|
|||||||
assign rxstopbit = rxshiftreg[0];
|
assign rxstopbit = rxshiftreg[0];
|
||||||
always_comb
|
always_comb
|
||||||
case(LCR[1:0]) // check how many bits used. Grab all bits including possible parity
|
case(LCR[1:0]) // check how many bits used. Grab all bits including possible parity
|
||||||
2'b00: rxdata9 = {3'b0, rxshiftreg[6:1]}; // 5-bit character
|
2'b00: rxdata9 = {3'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6]}; // 5-bit character
|
||||||
2'b01: rxdata9 = {2'b0, rxshiftreg[7:1]}; // 6-bit
|
2'b01: rxdata9 = {2'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7]}; // 6-bit
|
||||||
2'b10: rxdata9 = {1'b0, rxshiftreg[8:1]}; // 7-bit
|
2'b10: rxdata9 = {1'b0, rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8]}; // 7-bit
|
||||||
2'b11: rxdata9 = rxshiftreg[9:1];
|
2'b11: rxdata9 = { rxshiftreg[1], rxshiftreg[2], rxshiftreg[3], rxshiftreg[4], rxshiftreg[5], rxshiftreg[6], rxshiftreg[7], rxshiftreg[8], rxshiftreg[9]}; // 8-bit
|
||||||
endcase
|
endcase
|
||||||
assign rxdata = LCR[3] ? rxdata9[8:1] : rxdata9[7:0]; // discard parity bit
|
assign rxdata = LCR[3] ? rxdata9[7:0] : rxdata9[8:1]; // discard parity bit
|
||||||
|
|
||||||
// ERROR CONDITIONS
|
// ERROR CONDITIONS
|
||||||
assign rxparity = ^rxdata;
|
assign rxparity = ^rxdata;
|
||||||
|
|||||||
@ -100,7 +100,7 @@ logic [3:0] dummy;
|
|||||||
"testsBP64": tests = testsBP64;
|
"testsBP64": tests = testsBP64;
|
||||||
"wally64i": tests = wally64i; // *** redo
|
"wally64i": tests = wally64i; // *** redo
|
||||||
"wally64priv": tests = wally64priv;// *** redo
|
"wally64priv": tests = wally64priv;// *** redo
|
||||||
"imperas64periph": tests = imperas64periph;
|
"wally64periph": tests = wally64periph;
|
||||||
"coremark": tests = coremark;
|
"coremark": tests = coremark;
|
||||||
endcase
|
endcase
|
||||||
end else begin // RV32
|
end else begin // RV32
|
||||||
@ -123,7 +123,6 @@ logic [3:0] dummy;
|
|||||||
"wally32i": tests = wally32i; // *** redo
|
"wally32i": tests = wally32i; // *** redo
|
||||||
"wally32e": tests = wally32e;
|
"wally32e": tests = wally32e;
|
||||||
"wally32priv": tests = wally32priv; // *** redo
|
"wally32priv": tests = wally32priv; // *** redo
|
||||||
"imperas32periph": tests = imperas32periph;
|
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
if (tests.size() == 0) begin
|
if (tests.size() == 0) begin
|
||||||
|
|||||||
@ -890,17 +890,6 @@ string imperas32f[] = '{
|
|||||||
"rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
|
"rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
|
||||||
};
|
};
|
||||||
|
|
||||||
string imperas64periph[] = '{
|
|
||||||
`MYIMPERASTEST,
|
|
||||||
"rv64i-periph/WALLY-PERIPH", "2000"
|
|
||||||
};
|
|
||||||
|
|
||||||
string imperas32periph[] = '{
|
|
||||||
`MYIMPERASTEST,
|
|
||||||
"rv32i-periph/WALLY-PLIC", "2080"
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
string arch64priv[] = '{
|
string arch64priv[] = '{
|
||||||
`RISCVARCHTEST,
|
`RISCVARCHTEST,
|
||||||
"rv64i_m/privilege/ebreak", "2090",
|
"rv64i_m/privilege/ebreak", "2090",
|
||||||
@ -1496,7 +1485,8 @@ string imperas32f[] = '{
|
|||||||
};
|
};
|
||||||
|
|
||||||
string wally64periph[] = '{
|
string wally64periph[] = '{
|
||||||
`WALLYTEST
|
`WALLYTEST,
|
||||||
|
"rv64i_m/privilege/WALLY-PERIPH", "3110"
|
||||||
};
|
};
|
||||||
|
|
||||||
string wally32e[] = '{
|
string wally32e[] = '{
|
||||||
|
|||||||
@ -38,7 +38,9 @@ rv64i_sc_tests = \
|
|||||||
WALLY-scratch-01 \
|
WALLY-scratch-01 \
|
||||||
WALLY-sscratch-s-01
|
WALLY-sscratch-s-01
|
||||||
|
|
||||||
target_tests_nosim = WALLY-PMA \
|
target_tests_nosim = \
|
||||||
|
WALLY-PMA \
|
||||||
|
WALLY-PERIPH
|
||||||
|
|
||||||
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
|
||||||
|
|
||||||
|
|||||||
@ -0,0 +1,432 @@
|
|||||||
|
01BEEF00
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000004
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
00000068
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
01BEEF01
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
00080000
|
||||||
|
00080000
|
||||||
|
00080000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00080000
|
||||||
|
00080000
|
||||||
|
FFFFFFFF
|
||||||
|
FFF7FFFF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
01BEEF02
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
00000001
|
||||||
|
00000001
|
||||||
|
00000001
|
||||||
|
00000000
|
||||||
|
00080000
|
||||||
|
00000000
|
||||||
|
00080001
|
||||||
|
00000001
|
||||||
|
FFFFFFFF
|
||||||
|
FFFFFFFE
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
01BEEF03
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000004
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
00000065
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF04
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
0000F0F0
|
||||||
|
3030F0F0
|
||||||
|
0000F0F0
|
||||||
|
00000000
|
||||||
|
00000001
|
||||||
|
00000000
|
||||||
|
0000F0F1
|
||||||
|
0000F0F0
|
||||||
|
FFFFFFFF
|
||||||
|
FFFF0F0F
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF05
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
30300000
|
||||||
|
3030F0F0
|
||||||
|
30300000
|
||||||
|
00000000
|
||||||
|
0000F0F0
|
||||||
|
00000000
|
||||||
|
3030F0F0
|
||||||
|
30300000
|
||||||
|
FFFFFFFF
|
||||||
|
CFCFFFFF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF06
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
30000000
|
||||||
|
3030F0F0
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00300000
|
||||||
|
00000000
|
||||||
|
30300000
|
||||||
|
30000000
|
||||||
|
CFFFFFFF
|
||||||
|
CFFFFFFF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF07
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
0F000000
|
||||||
|
0F0F0F0F
|
||||||
|
0F000000
|
||||||
|
00000000
|
||||||
|
30000000
|
||||||
|
00000000
|
||||||
|
3F000000
|
||||||
|
0F000000
|
||||||
|
FFFFFFFF
|
||||||
|
F0FFFFFF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF08
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
00FFFF00
|
||||||
|
00FFFF00
|
||||||
|
00FFFF00
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00FFFF00
|
||||||
|
00FFFF00
|
||||||
|
FFFFFFFF
|
||||||
|
FF0000FF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF09
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
33FFFF33
|
||||||
|
33FFFF33
|
||||||
|
33000033
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
33FFFF33
|
||||||
|
33FFFF33
|
||||||
|
FF0000FF
|
||||||
|
CC0000CC
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF0A
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
33000033
|
||||||
|
33000033
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00FFFF00
|
||||||
|
00000000
|
||||||
|
33FFFF33
|
||||||
|
33000033
|
||||||
|
CCFFFFCC
|
||||||
|
CCFFFFCC
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF0B
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
00CCCC00
|
||||||
|
00CCCC00
|
||||||
|
00CCCC00
|
||||||
|
00000000
|
||||||
|
33000033
|
||||||
|
00000000
|
||||||
|
33CCCC33
|
||||||
|
00CCCC00
|
||||||
|
FFFFFFFF
|
||||||
|
FF3333FF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF0C
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
00CCCC00
|
||||||
|
00CCCC00
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00CCCC00
|
||||||
|
00CCCC00
|
||||||
|
FF3333FF
|
||||||
|
FF3333FF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF0D
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
CC00CCCC
|
||||||
|
CCCCCCCC
|
||||||
|
CC00CCCC
|
||||||
|
00000000
|
||||||
|
00CCCC00
|
||||||
|
00000000
|
||||||
|
CC00CCCC
|
||||||
|
CC00CCCC
|
||||||
|
FFFFFFFF
|
||||||
|
33FF3333
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF0E
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
CCCCCCCC
|
||||||
|
CCCCCCCC
|
||||||
|
00CC0000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
CCCCCCCC
|
||||||
|
CCCCCCCC
|
||||||
|
33FF3333
|
||||||
|
33333333
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF0F
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
000011FF
|
||||||
|
FF1111FF
|
||||||
|
33333333
|
||||||
|
00000000
|
||||||
|
FFFFEE00
|
||||||
|
00000000
|
||||||
|
FFFFFFFF
|
||||||
|
000011FF
|
||||||
|
FFFFEE00
|
||||||
|
FFFFEE00
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF10
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
000000FF
|
||||||
|
FFFFFFFF
|
||||||
|
000000FF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
000000FF
|
||||||
|
000000FF
|
||||||
|
FFFFFFFF
|
||||||
|
FFFFFF00
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
02BEEF11
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
00000003
|
||||||
|
000000CC
|
||||||
|
CCCCCCCC
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000033
|
||||||
|
00000000
|
||||||
|
000000FF
|
||||||
|
000000CC
|
||||||
|
FFFFFF33
|
||||||
|
FFFFFF33
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF12
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000002
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
0000006C
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF13
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000002
|
||||||
|
00000021
|
||||||
|
00000021
|
||||||
|
0000006C
|
||||||
|
00000020
|
||||||
|
00000001
|
||||||
|
00000002
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF14
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000004
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
0000006F
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF15
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000004
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
00000020
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000003
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF16
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000004
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
00000074
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000020
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF17
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000002
|
||||||
|
00000020
|
||||||
|
00000020
|
||||||
|
00000074
|
||||||
|
00000020
|
||||||
|
00000001
|
||||||
|
00000003
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF18
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000002
|
||||||
|
00000020
|
||||||
|
00000020
|
||||||
|
00000074
|
||||||
|
00000020
|
||||||
|
00000001
|
||||||
|
00000003
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF19
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000004
|
||||||
|
00000061
|
||||||
|
00000061
|
||||||
|
00000065
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
00000003
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
03BEEF1A
|
||||||
|
0000000B
|
||||||
|
80000000
|
||||||
|
0000000A
|
||||||
|
00000006
|
||||||
|
00000063
|
||||||
|
00000061
|
||||||
|
00000047
|
||||||
|
00000060
|
||||||
|
00000001
|
||||||
|
000000FF
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
|
00000000
|
||||||
@ -0,0 +1,820 @@
|
|||||||
|
///////////////////////////////////////////
|
||||||
|
// WALLY-PERIPH.S
|
||||||
|
// 64 bit version
|
||||||
|
//
|
||||||
|
// Ben Bracker (bbracker@hmc.edu)
|
||||||
|
//
|
||||||
|
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||||
|
// Adapted from Imperas RISCV-TEST_SUITE
|
||||||
|
//
|
||||||
|
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||||
|
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||||
|
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||||
|
// is furnished to do so, subject to the following conditions:
|
||||||
|
//
|
||||||
|
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||||
|
//
|
||||||
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||||
|
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||||
|
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
///////////////////////////////////////////
|
||||||
|
|
||||||
|
#include "model_test.h"
|
||||||
|
#include "arch_test.h"
|
||||||
|
|
||||||
|
RVTEST_ISA("RV64I")
|
||||||
|
|
||||||
|
.section .text.init
|
||||||
|
.globl rvtest_entry_point
|
||||||
|
rvtest_entry_point:
|
||||||
|
RVMODEL_BOOT
|
||||||
|
RVTEST_CODE_BEGIN
|
||||||
|
|
||||||
|
# ---------------------------------------------------------------------------------------------
|
||||||
|
j main_code
|
||||||
|
|
||||||
|
###################
|
||||||
|
###################
|
||||||
|
trap_handler: #####
|
||||||
|
###################
|
||||||
|
###################
|
||||||
|
# save registers
|
||||||
|
addi sp, sp, 0x20
|
||||||
|
sw t0, 0x00(sp)
|
||||||
|
sw t1, 0x08(sp)
|
||||||
|
sw t2, 0x10(sp)
|
||||||
|
sw t3, 0x18(sp)
|
||||||
|
|
||||||
|
# ===================================
|
||||||
|
# ===== Signature Output Format =====
|
||||||
|
# ===================================
|
||||||
|
#
|
||||||
|
# Base address = <wally_signature>+0x40*<intr_num>
|
||||||
|
# Use sigout-translator.py for help with this!
|
||||||
|
#
|
||||||
|
# <offset>: <contents>
|
||||||
|
# 0x00: test ID = 0x<group_num>BEEF<intr_num>
|
||||||
|
# 0x04: mcause (low) = 0x0000000B
|
||||||
|
# 0x08: mcause (high) = 0x80000000
|
||||||
|
# ----- If GPIO -----
|
||||||
|
# 0x0C: claim ID = 3
|
||||||
|
# 0x10: input_val
|
||||||
|
# 0x14: output_val
|
||||||
|
# 0x18: incoming rise_ip
|
||||||
|
# 0x1C: serviced rise_ip = 0
|
||||||
|
# 0x20: incoming fall_ip
|
||||||
|
# 0x24: serviced fall_ip = 0
|
||||||
|
# 0x28: incoming high_ip
|
||||||
|
# 0x2C: serviced high_ip = 0
|
||||||
|
# 0x30: incoming low_ip
|
||||||
|
# 0x34: serviced low_ip = 0
|
||||||
|
# ----- If UART -----
|
||||||
|
# 0x0C: claim ID = 0xA
|
||||||
|
# 0x10: IIR
|
||||||
|
# 0x14: LSR
|
||||||
|
# 0x18: LSR (after reading LSR)
|
||||||
|
# 0x1C: RBR
|
||||||
|
# 0x20: LSR (after reading RBR too)
|
||||||
|
# 0x24: IIR (after reading everything else)
|
||||||
|
# 0x28: SCR
|
||||||
|
|
||||||
|
# 0x00: test ID = 0x<group_num>BEEF<intr_num>
|
||||||
|
la t0, wally_signature
|
||||||
|
sub t0, s0, t0 # sigout offset
|
||||||
|
srli t0, t0, 6 # intr_num
|
||||||
|
add t0, t0, a1
|
||||||
|
sw t0, 0x00(s0)
|
||||||
|
|
||||||
|
# 0x04: mcause (low) = 0x0000000B
|
||||||
|
# 0x08: mcause (high) = 0x80000000
|
||||||
|
# Expect interrupt from src 11 (machine external interrupt)
|
||||||
|
csrrc t1, mcause, x0
|
||||||
|
sw t1, 0x04(s0)
|
||||||
|
srli t1,t1,32
|
||||||
|
sw t1, 0x08(s0)
|
||||||
|
|
||||||
|
# 0x: claim ID
|
||||||
|
# 3: GPIO
|
||||||
|
# A: UART
|
||||||
|
li t0, 0x0C200004
|
||||||
|
lw t1, 0(t0)
|
||||||
|
sw t1, 0x0C(s0)
|
||||||
|
li t2, 0xA
|
||||||
|
beq t1, t2, uart_handler
|
||||||
|
li t2, 3
|
||||||
|
bne t1, t2, trap_handler_end
|
||||||
|
|
||||||
|
gpio_handler:
|
||||||
|
# 0x10: input_val
|
||||||
|
li t0, 0x10060000
|
||||||
|
lw t1, 0x00(t0)
|
||||||
|
sw t1, 0x10(s0)
|
||||||
|
# 0x14: output_val
|
||||||
|
lw t1, 0x0C(t0)
|
||||||
|
sw t1, 0x14(s0)
|
||||||
|
# 0x18: incoming rise_ip
|
||||||
|
lw t1, 0x1C(t0)
|
||||||
|
sw t1, 0x18(s0)
|
||||||
|
# 0x1C: serviced rise_ip = 0
|
||||||
|
sw t1, 0x1C(t0)
|
||||||
|
lw t1, 0x1C(t0)
|
||||||
|
sw t1, 0x1C(s0)
|
||||||
|
# 0x20: incoming fall_ip
|
||||||
|
lw t1, 0x24(t0)
|
||||||
|
sw t1, 0x20(s0)
|
||||||
|
# 0x24: serviced fall_ip = 0
|
||||||
|
sw t1, 0x24(t0)
|
||||||
|
lw t1, 0x24(t0)
|
||||||
|
sw t1, 0x24(s0)
|
||||||
|
# 0x28: incoming high_ip
|
||||||
|
lw t1, 0x2C(t0)
|
||||||
|
sw t1, 0x28(s0)
|
||||||
|
# 0x2C: serviced high_ip = 0
|
||||||
|
sw t1, 0x2C(t0)
|
||||||
|
lw t1, 0x2C(t0)
|
||||||
|
sw t1, 0x2C(s0)
|
||||||
|
# 0x30: incoming low_ip
|
||||||
|
lw t1, 0x34(t0)
|
||||||
|
sw t1, 0x30(s0)
|
||||||
|
# 0x34: serviced low_ip = 0
|
||||||
|
sw t1, 0x34(t0)
|
||||||
|
lw t1, 0x34(t0)
|
||||||
|
sw t1, 0x34(s0)
|
||||||
|
# disable high_ie and low_ie so interrupt
|
||||||
|
# is not taken again immediately
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
sw t1, 0x30(t0)
|
||||||
|
# signal to main code that gpio was serviced
|
||||||
|
ori a0, a0, 0b00001000
|
||||||
|
# signal to plic that gpio was serviced
|
||||||
|
li t0, 0x0C200004
|
||||||
|
li t1, 3
|
||||||
|
sw t1, 0(t0)
|
||||||
|
j trap_handler_end
|
||||||
|
|
||||||
|
uart_handler:
|
||||||
|
# 0x10: IIR
|
||||||
|
li t0, 0x10000000
|
||||||
|
lbu t1, 2(t0)
|
||||||
|
sw t1, 0x10(s0)
|
||||||
|
# 0x14: LSR
|
||||||
|
lbu t1, 5(t0)
|
||||||
|
sw t1, 0x14(s0)
|
||||||
|
# 0x18: LSR (after reading LSR)
|
||||||
|
lbu t1, 5(t0)
|
||||||
|
sw t1, 0x18(s0)
|
||||||
|
# 0x1C: RBR
|
||||||
|
lbu t1, 0(t0)
|
||||||
|
sw t1, 0x1C(s0)
|
||||||
|
# 0x20: LSR (after reading RBR)
|
||||||
|
lbu t1, 5(t0)
|
||||||
|
sw t1, 0x20(s0)
|
||||||
|
# 0x24: IIR (after reading everything else)
|
||||||
|
lbu t1, 2(t0)
|
||||||
|
sw t1, 0x24(s0)
|
||||||
|
# 0x28: SCR
|
||||||
|
lbu t1, 7(t0)
|
||||||
|
sw t1, 0x28(s0)
|
||||||
|
# signal to main code that uart was serviced
|
||||||
|
ori a0, a0, 0b00010000
|
||||||
|
# signal to plic that uart was serviced
|
||||||
|
li t0, 0x0C200004
|
||||||
|
li t1, 0xA
|
||||||
|
sw t1, 0(t0)
|
||||||
|
|
||||||
|
trap_handler_end:
|
||||||
|
# increment signature pointer
|
||||||
|
addi s0,s0,0x40
|
||||||
|
# restore vars
|
||||||
|
ld t0, 0x00(sp)
|
||||||
|
ld t1, 0x08(sp)
|
||||||
|
ld t2, 0x10(sp)
|
||||||
|
ld t3, 0x18(sp)
|
||||||
|
addi sp, sp, SEXT_IMM(-0x20)
|
||||||
|
mret
|
||||||
|
|
||||||
|
################
|
||||||
|
################
|
||||||
|
main_code: #####
|
||||||
|
################
|
||||||
|
################
|
||||||
|
|
||||||
|
##########################
|
||||||
|
##### Initialization #####
|
||||||
|
##########################
|
||||||
|
# ========== Global Vars ==========
|
||||||
|
la s0, wally_signature # signature output base adr
|
||||||
|
la sp, stack # stack pointer
|
||||||
|
li a0, 0 # interrupt complete flag
|
||||||
|
# ========== Configure Privileged Unit ==========
|
||||||
|
# load address of trap handler
|
||||||
|
la t0, trap_handler
|
||||||
|
csrrw x0, mtvec, t0
|
||||||
|
# delegate all external interrupts to machine mode
|
||||||
|
li t0, 0xD00
|
||||||
|
csrrc x0, mideleg, t0
|
||||||
|
# set MIE
|
||||||
|
li t0, 0x8
|
||||||
|
csrrs x0, mstatus, t0
|
||||||
|
|
||||||
|
##################################
|
||||||
|
##### Test 1 - Signs of Life #####
|
||||||
|
##################################
|
||||||
|
li a1, 0x01beef00 # group ID
|
||||||
|
# clear MEIE (good to turn off while configuring peripherals)
|
||||||
|
li t0, 0x800
|
||||||
|
csrrc x0, mie, t0
|
||||||
|
# ========== Configure PLIC ==========
|
||||||
|
# priority threshold = 0
|
||||||
|
li t0, 0xC200000
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0(t0)
|
||||||
|
# source 3 (GPIO) priority = 6
|
||||||
|
li t0, 0xC000000
|
||||||
|
li t1, 6
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# source 0xA (UART) priority = 7
|
||||||
|
li t1, 7
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
# enable sources 3,0xA
|
||||||
|
li t0, 0x0C002000
|
||||||
|
li t1, 0b10000001000
|
||||||
|
sw t1, 0(t0)
|
||||||
|
# ========== Configure UART ==========
|
||||||
|
# MCR: Loop = 1
|
||||||
|
li t0, 0x10000000
|
||||||
|
li t1, 0b10000
|
||||||
|
sb t1, 4(t0)
|
||||||
|
# LCR: Use 8 data bits plus odd parity bit
|
||||||
|
li t1, 0b00001011
|
||||||
|
sb t1, 3(t0)
|
||||||
|
# IER: Enable Received Data Available Interrupt
|
||||||
|
li t1, 0x01
|
||||||
|
sb t1, 1(t0)
|
||||||
|
# ========== Configure GPIO ==========
|
||||||
|
# raise all input_en
|
||||||
|
li t0, 0x10060000
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# raise all output_en
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# raise all input_en
|
||||||
|
sw t1, 0x18(t0)
|
||||||
|
# ========== Execute Test ==========
|
||||||
|
# set MEIE
|
||||||
|
li t0, 0x800
|
||||||
|
csrrs x0, mie, t0
|
||||||
|
Intr01BEEF01:
|
||||||
|
# UART TX 'h'
|
||||||
|
li t0, 0x10000000
|
||||||
|
li t1, 'h'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
Intr01BEEF02:
|
||||||
|
# GPIO raise pin 19
|
||||||
|
li t0, 0x10060000
|
||||||
|
li t1, 0x00080000
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# Now let's go bonkers and trigger both!
|
||||||
|
Intr01BEEF03:
|
||||||
|
# TX 'e'
|
||||||
|
li t0, 0x10000000
|
||||||
|
li t1, 'e'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
Intr01BEEF04:
|
||||||
|
# GPIO lower pin 19 raise pin 0
|
||||||
|
li t0, 0x10060000
|
||||||
|
li t1, 0x00000001
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00011000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
|
||||||
|
##################################
|
||||||
|
##### Test 2 - GPIO Testing #####
|
||||||
|
##################################
|
||||||
|
li a1, 0x02beef00 # group ID
|
||||||
|
# clear MEIE
|
||||||
|
li t0, 0x800
|
||||||
|
csrrc x0, mie, t0
|
||||||
|
# ========== Configure PLIC ==========
|
||||||
|
# priority threshold = 0
|
||||||
|
li t0, 0xC200000
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0(t0)
|
||||||
|
# source 3 (GPIO) priority = 1
|
||||||
|
li t0, 0xC000000
|
||||||
|
li t1, 1
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# enable source 3
|
||||||
|
li t0, 0x0C002000
|
||||||
|
li t1, 0b1000
|
||||||
|
sw t1, 0(t0)
|
||||||
|
# ========== Input Enables ==========
|
||||||
|
# Note that this inherits
|
||||||
|
# a bit of state from the previous test.
|
||||||
|
# Namely output_val = 0x00000001
|
||||||
|
#
|
||||||
|
# enable some inputs
|
||||||
|
li t0, 0x10060000
|
||||||
|
li t1, 0x0000FFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# enable all outputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# enable all rising edge interrupts
|
||||||
|
sw t1, 0x18(t0)
|
||||||
|
# set MEIE
|
||||||
|
li t1, 0x800
|
||||||
|
csrrs x0, mie, t1
|
||||||
|
# raise some input-disabled pins
|
||||||
|
# interrupt should not happen
|
||||||
|
li t1, 0xF0F00001
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
Intr02BEEF04:
|
||||||
|
# change some input-enabled pins
|
||||||
|
# interrupt should happen
|
||||||
|
li t1, 0x3030F0F0
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
Intr02BEEF05:
|
||||||
|
# enable some different inputs
|
||||||
|
# this itself will cause some rise interrupts
|
||||||
|
li t1, 0xFFFF0000
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ========== Output Enables ==========
|
||||||
|
# enable all fall interrupts
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x20(t0)
|
||||||
|
Intr02BEEF06:
|
||||||
|
# disable some outputs
|
||||||
|
# should affect input value but not output val register itself
|
||||||
|
# this itself will cause some fall interrupts
|
||||||
|
li t1, 0xFF0000FF
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# change pins whose inputs and/or outputs are disabled
|
||||||
|
# should not cause any rise or fall interrupts
|
||||||
|
li t1, 0x300F0F0F
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
Intr02BEEF07:
|
||||||
|
# change pins whose inputs and outputs are enabled
|
||||||
|
li t1, 0x0F0F0F0F
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ========== Clear GPIO State ==========
|
||||||
|
# (I've gotten a little annoyed with tests depending
|
||||||
|
# upon the results of previous tests).
|
||||||
|
# disable all interrupts
|
||||||
|
sw x0, 0x18(t0)
|
||||||
|
sw x0, 0x20(t0)
|
||||||
|
sw x0, 0x28(t0)
|
||||||
|
sw x0, 0x30(t0)
|
||||||
|
# enable all inputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# enable all outputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# set initial output state
|
||||||
|
sw x0, 0x0C(t0)
|
||||||
|
# clear all pending interrupts
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x1C(t0)
|
||||||
|
sw t1, 0x24(t0)
|
||||||
|
sw t1, 0x2C(t0)
|
||||||
|
sw t1, 0x34(t0)
|
||||||
|
# ========== Rise Interrupt Enables ==========
|
||||||
|
# enable some rising edge interrupts
|
||||||
|
li t1, 0x0000FFFF
|
||||||
|
sw t1, 0x18(t0)
|
||||||
|
Intr02BEEF08:
|
||||||
|
# raise some pins
|
||||||
|
li t1, 0x00FFFF00
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
Intr02BEEF09:
|
||||||
|
# raise pins whose rise IEs are disabled
|
||||||
|
# should not cause an interrupt
|
||||||
|
li t1, 0x33FFFF00
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# raise pins whose rise IEs are enabled
|
||||||
|
li t1, 0x33FFFF33
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# =========== Fall Interrupts ===========
|
||||||
|
# (admittedly these are already used elsewhere)
|
||||||
|
# disable all rising edge interrupts
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0x18(t0)
|
||||||
|
# enable some falling edge interrupts
|
||||||
|
li t1, 0x0000FFFF
|
||||||
|
sw t1, 0x20(t0)
|
||||||
|
Intr02BEEF0A:
|
||||||
|
# lower some pins
|
||||||
|
li t1, 0x33000033
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# lower pins whose fall IEs are disabled
|
||||||
|
# and raise a bunch of other pins
|
||||||
|
# should not cause an interrupt
|
||||||
|
li t1, 0x00CCCC33
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
Intr02BEEF0B:
|
||||||
|
# lower pins whose fall IEs are enabled
|
||||||
|
li t1, 0x00CCCC00
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# =========== High Interrupts ===========
|
||||||
|
# disable all falling edge interrupts
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0x20(t0)
|
||||||
|
# enable some high_ie's for low pins
|
||||||
|
# should not cause an interrupt
|
||||||
|
li t1, 0xFF0000FF
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
Intr02BEEF0C:
|
||||||
|
# enable some high_ie's for high pins
|
||||||
|
li t1, 0x0000FFFF
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# lower all pins
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# lower any existing high_ip's
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x2C(t0)
|
||||||
|
# re-enable some high_ie's
|
||||||
|
li t1, 0xFFFF0000
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
# raise some pins whose high_ie's are disabled
|
||||||
|
li t1, 0x0000CCCC
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# disable some inputs
|
||||||
|
li t1, 0xFF00FFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# raise some pins whose inputs are disabled
|
||||||
|
li t1, 0x00CCCCCC
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
Intr02BEEF0D:
|
||||||
|
# raise some pins whose high_ie's and inputs are enabled
|
||||||
|
li t1, 0xCCCCCCCC
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# =========== Low Interrupts ===========
|
||||||
|
# disable all high interrupts
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
# enable all inputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# enable some low_ie's for high pins
|
||||||
|
# should not cause an interrupt
|
||||||
|
li t1, 0xCC0000CC
|
||||||
|
sw t1, 0x30(t0)
|
||||||
|
Intr02BEEF0E:
|
||||||
|
# enable some low_ie's for low pins
|
||||||
|
li t1, 0xCCCCFFFF
|
||||||
|
sw t1, 0x30(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# raise all pins
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
# lower any existing low_ip's
|
||||||
|
# actually takes a little time for vals
|
||||||
|
# to propagate through synchronizer
|
||||||
|
# so this extra load is a nop effectively
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x34(t0)
|
||||||
|
# re-enable some low_ie's
|
||||||
|
li t1, 0xFF0000FF
|
||||||
|
sw t1, 0x30(t0)
|
||||||
|
# lower some pins whose low_ie's are disabled
|
||||||
|
li t1, 0xFF1111FF
|
||||||
|
sw t1, 0x0C(t0)
|
||||||
|
Intr02BEEF0F:
|
||||||
|
# disable some inputs of pins whose low_ie's are enabled
|
||||||
|
li t1, 0x0000FFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ========== Clear GPIO State ==========
|
||||||
|
# disable all interrupts
|
||||||
|
sw x0, 0x18(t0)
|
||||||
|
sw x0, 0x20(t0)
|
||||||
|
sw x0, 0x28(t0)
|
||||||
|
sw x0, 0x30(t0)
|
||||||
|
# enable all inputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# enable all outputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# set initial output state
|
||||||
|
sw x0, 0x0C(t0)
|
||||||
|
# clear all pending interrupts
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x1C(t0)
|
||||||
|
sw t1, 0x24(t0)
|
||||||
|
sw t1, 0x2C(t0)
|
||||||
|
sw t1, 0x34(t0)
|
||||||
|
# ========== Output XOR Test ==========
|
||||||
|
# enable some inputs
|
||||||
|
li t1, 0x0000FFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# enable some outputs
|
||||||
|
li t1, 0xFF0000FF
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# enable all rising and falling edge interrupts
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x18(t0)
|
||||||
|
sw t1, 0x20(t0)
|
||||||
|
Intr02BEEF10:
|
||||||
|
# XOR all outputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x40(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
Intr02BEEF11:
|
||||||
|
# XOR some outputs
|
||||||
|
li t1, 0x33333333
|
||||||
|
sw t1, 0x40(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00001000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ========== Clear GPIO State ==========
|
||||||
|
# disable all interrupts
|
||||||
|
sw x0, 0x18(t0)
|
||||||
|
sw x0, 0x20(t0)
|
||||||
|
sw x0, 0x28(t0)
|
||||||
|
sw x0, 0x30(t0)
|
||||||
|
# enable all inputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x04(t0)
|
||||||
|
# enable all outputs
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x08(t0)
|
||||||
|
# set initial output state
|
||||||
|
sw x0, 0x0C(t0)
|
||||||
|
# clear all pending interrupts
|
||||||
|
li t1, 0xFFFFFFFF
|
||||||
|
sw t1, 0x1C(t0)
|
||||||
|
sw t1, 0x24(t0)
|
||||||
|
sw t1, 0x2C(t0)
|
||||||
|
sw t1, 0x34(t0)
|
||||||
|
|
||||||
|
##################################
|
||||||
|
##### Test 3 - UART Testing #####
|
||||||
|
##################################
|
||||||
|
li a1, 0x03beef00 # group ID
|
||||||
|
# clear MEIE
|
||||||
|
li t0, 0x800
|
||||||
|
csrrc x0, mie, t0
|
||||||
|
# ========== Configure PLIC ==========
|
||||||
|
# priority threshold = 0
|
||||||
|
li t0, 0xC200000
|
||||||
|
li t1, 0
|
||||||
|
sw t1, 0(t0)
|
||||||
|
# source 0xA (UART) priority = 1
|
||||||
|
li t0, 0xC000000
|
||||||
|
li t1, 1
|
||||||
|
sw t1, 0x28(t0)
|
||||||
|
# enable source 0xA
|
||||||
|
li t0, 0x0C002000
|
||||||
|
li t1, 0b10000000000
|
||||||
|
sw t1, 0(t0)
|
||||||
|
# ========== Transmitter Holding Register Empty Interrupt (THRE) ==========
|
||||||
|
# MCR: Loop = 1
|
||||||
|
li t0, 0x10000000
|
||||||
|
li t1, 0b00010000
|
||||||
|
sb t1, 4(t0)
|
||||||
|
# LCR: Use 8 data bits plus odd parity bit
|
||||||
|
li t1, 0b00001011
|
||||||
|
sb t1, 3(t0)
|
||||||
|
# IER: Disable all interrupts for now
|
||||||
|
li t1, 0x0
|
||||||
|
sb t1, 1(t0)
|
||||||
|
# set MEIE
|
||||||
|
li t1, 0x800
|
||||||
|
csrrs x0, mie, t1
|
||||||
|
# THR: TX 'l'
|
||||||
|
li t1, 'l'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# wait directly on UART for completion
|
||||||
|
li t1, 0b01100001
|
||||||
|
1: lb t2, 5(t0)
|
||||||
|
bne t1, t2, 1b
|
||||||
|
Intr03BEEF12:
|
||||||
|
# IER: enable THR empty intr (ETBEI)
|
||||||
|
li t1, 0b00000010
|
||||||
|
sb t1, 1(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# IER: disable THR empty intr (ETBEI)
|
||||||
|
sb x0, 1(t0)
|
||||||
|
# THR: TX 'l'
|
||||||
|
li t1, 'l'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# THR: TX 'o'
|
||||||
|
li t1, 'o'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
Intr03BEEF13:
|
||||||
|
# IER: enable THR empty intr (ETBEI)
|
||||||
|
li t1, 0b00000010
|
||||||
|
sb t1, 1(t0)
|
||||||
|
# This will take a few cycles before UART finishes TX'ing
|
||||||
|
# If we see SCR modifications in output, it means UART probably
|
||||||
|
# did wait until empty THR before triggering the interrupt.
|
||||||
|
sb t1, 7(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ==========
|
||||||
|
# Clear SCR
|
||||||
|
sb x0, 7(t0)
|
||||||
|
Intr03BEEF14:
|
||||||
|
# IER: enable RBR ready intr ERBFI
|
||||||
|
li t1, 0x1
|
||||||
|
sb t1, 1(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
Intr03BEEF15:
|
||||||
|
# THR: TX ' '
|
||||||
|
li t1, 0x20
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# This will take a few cycles before UART finishes RX'ing
|
||||||
|
# If we see SCR modifications in output, it means UART probably
|
||||||
|
# did wait until received data available before triggering the interrupt.
|
||||||
|
li t1, 3
|
||||||
|
sb t1, 7(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
Intr03BEEF16:
|
||||||
|
# THR: TX 't'
|
||||||
|
li t1, 't'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# Same shenanigans as before, only now we also confirm
|
||||||
|
# that you can read the RBR before new data is available
|
||||||
|
# without messing up the receive interrupt.
|
||||||
|
lb t1, 0(t0)
|
||||||
|
sb t1, 7(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# MCR: Loop = 0
|
||||||
|
li t1, 0b00000000
|
||||||
|
sb t1, 4(t0)
|
||||||
|
# Clear SCR
|
||||||
|
sb x0, 7(t0)
|
||||||
|
# THR: TX 'h'
|
||||||
|
# should TX but not not trigger interrupt
|
||||||
|
li t1, 'h'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# wait directly on UART for completion
|
||||||
|
li t1, 0b01100000
|
||||||
|
1: lb t2, 5(t0)
|
||||||
|
bne t1, t2, 1b
|
||||||
|
# Can use THRE test from before to verify we are transmitting
|
||||||
|
# THR: TX 'e'
|
||||||
|
li t1, 'e'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# THR: TX 'r'
|
||||||
|
li t1, 'r'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
Intr03BEEF17:
|
||||||
|
# IER: enable THR empty intr (ETBEI) and RBR ready intr (ERBFI)
|
||||||
|
li t1, 0b00000011
|
||||||
|
sb t1, 1(t0)
|
||||||
|
sb t1, 7(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# manually wait until transmitter finishes before enabling loop mode
|
||||||
|
li t1, 0b01100000
|
||||||
|
1: lb t2, 5(t0)
|
||||||
|
bne t1, t2, 1b
|
||||||
|
# MCR: Loop = 1
|
||||||
|
li t1, 0b00010000
|
||||||
|
sb t1, 4(t0)
|
||||||
|
Intr03BEEF18:
|
||||||
|
Intr03BEEF19:
|
||||||
|
# THR: TX 'e'
|
||||||
|
li t1, 'e'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# wait to finish again
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ========== Receiver Line Status Intr (ELSI) & Overrun Error (OE) ==========
|
||||||
|
# IER: Enable Receiver Line Status Intr (ELSI)
|
||||||
|
li t1, 0b00000100
|
||||||
|
sb t1, 1(t0)
|
||||||
|
li t1, 0xFF
|
||||||
|
sb t1, 7(t0)
|
||||||
|
# We can't cause all kinds of interesting errors, but at least we can
|
||||||
|
# cause an overrun error by transmitting twice without reading.
|
||||||
|
Intr03BEEF1A:
|
||||||
|
# THR: TX '\n'
|
||||||
|
li t1, 0xD
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# THR: TX 'G'
|
||||||
|
li t1, 'G'
|
||||||
|
sb t1, 0(t0)
|
||||||
|
# wait to finish
|
||||||
|
li t1, 0b00010000
|
||||||
|
1: bne t1,a0,1b
|
||||||
|
li a0, 0
|
||||||
|
# ---------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
//terminate_test:
|
||||||
|
// li a0, 2 // Trap handler behavior (go to machine mode)
|
||||||
|
// ecall // writes mcause to the output.
|
||||||
|
// csrw mtvec, x4 // restore original trap handler to halt program
|
||||||
|
|
||||||
|
RVTEST_CODE_END
|
||||||
|
RVMODEL_HALT
|
||||||
|
|
||||||
|
RVTEST_DATA_BEGIN
|
||||||
|
# stack memory (size 16 words)
|
||||||
|
.align 3
|
||||||
|
stack:
|
||||||
|
.fill 16, 8, 0xdeadbeef
|
||||||
|
RVTEST_DATA_END
|
||||||
|
|
||||||
|
RVMODEL_DATA_BEGIN
|
||||||
|
# signature output
|
||||||
|
wally_signature:
|
||||||
|
.fill 0x200, 8, 0x00000000
|
||||||
|
|
||||||
|
#ifdef rvtest_mtrap_routine
|
||||||
|
mtrap_sigptr:
|
||||||
|
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef rvtest_gpr_save
|
||||||
|
gpr_save:
|
||||||
|
.fill 32*(XLEN/32),4,0xdeadbeef
|
||||||
|
#endif
|
||||||
|
RVMODEL_DATA_END
|
||||||
@ -0,0 +1,23 @@
|
|||||||
|
#!/usr/bin/env python3
|
||||||
|
if __name__ == "__main__":
|
||||||
|
import sys
|
||||||
|
if (('-h' in sys.argv) or ('--help' in sys.argv)):
|
||||||
|
helptxt = "This script helps to develop WALLY-PERIPH.S\n" \
|
||||||
|
"Give it a physical address such as 80002084,\n" \
|
||||||
|
"and it describes where that address is the signature output."
|
||||||
|
print(helptxt)
|
||||||
|
else:
|
||||||
|
adr = str(input("Address: "))
|
||||||
|
try:
|
||||||
|
adr = int(adr,16)
|
||||||
|
except:
|
||||||
|
exit("Oi that was not a valid address.")
|
||||||
|
base_adr = int("80002000",16)
|
||||||
|
sig_adr = adr-base_adr
|
||||||
|
line_num = int(sig_adr / 4) + 1
|
||||||
|
offset = sig_adr & 0x3F
|
||||||
|
test_num = int((sig_adr-offset)/int("40",16))
|
||||||
|
print("IntrNum 0x{:02X}".format(test_num))
|
||||||
|
print("Offset 0x{:02X}".format(offset))
|
||||||
|
print("LineNum "+str(line_num))
|
||||||
|
|
||||||
Loading…
Reference in New Issue
Block a user