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comment cleanup
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@ -61,8 +61,8 @@ module fdivsqrtfsm(
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// *** start logic is presently in fctl. Make it look more like integer division start logic
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// *** start logic is presently in fctl. Make it look more like integer division start logic
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// DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
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// DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
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assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
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assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
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assign DivDone = (state == DONE) | (WZero & (state == BUSY));
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assign DivDone = (state == DONE) | (WZero & (state == BUSY)); // *** used in postprocess.sv and round.sv. This doesn't seem proper. They break when removed.
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assign FDivBusyE = (state == BUSY & ~DivDone);
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assign FDivBusyE = (state == BUSY & ~DivDone); // *** want to add | DivStartE but it creates comb loop
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// Divider control signals from MDU
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// Divider control signals from MDU
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//assign DivBusyE = (state == BUSY) | DivStartE;
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//assign DivBusyE = (state == BUSY) | DivStartE;
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@ -129,7 +129,7 @@ module postprocess (
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assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
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assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
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assign CvtOp = (PostProcSel == 2'b00);
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assign CvtOp = (PostProcSel == 2'b00);
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assign FmaOp = (PostProcSel == 2'b10);
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assign FmaOp = (PostProcSel == 2'b10);
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assign DivOp = (PostProcSel == 2'b01)&DivDone;
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assign DivOp = (PostProcSel == 2'b01) & DivDone;
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assign Sqrt = OpCtrl[0];
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assign Sqrt = OpCtrl[0];
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// is there an input of infinity or NaN being used
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// is there an input of infinity or NaN being used
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