mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
This commit is contained in:
commit
58eed1bba2
@ -90,14 +90,14 @@ module fctrl (
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(Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED));
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(Fmt2 == 2'b10 & `ZFH_SUPPORTED) | (Fmt2 == 2'b11 & `Q_SUPPORTED));
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// decode the instruction
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// decode the instruction
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// ControlsD: FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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always_comb
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
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else begin
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else begin
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ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1_0; // default: illegal FPU instruction
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // default: non-implemented instruction
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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case(OpD)
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case(OpD)
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7'b0000111: case(Funct3D)
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7'b0000111: case(Funct3D)
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@ -146,13 +146,10 @@ module fctrl (
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
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ControlsD = `FCTRLW'b1_0_01_00_001_0_0_0; // fcvt.d.(s/h/q)
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// coverage off
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// We are turning off coverage because rv64gc configuration doesn't support quad or half
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7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
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7'b0100010: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b10)
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ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q)
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ControlsD = `FCTRLW'b1_0_01_00_010_0_0_0; // fcvt.h.(s/d/q)
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7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
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7'b0100011: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b11)
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ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d)
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ControlsD = `FCTRLW'b1_0_01_00_011_0_0_0; // fcvt.q.(s/h/d)
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// coverage on
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7'b1101000: case(Rs2D)
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7'b1101000: case(Rs2D)
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.s.w w->s
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.s.wu wu->s
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@ -177,9 +174,6 @@ module fctrl (
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.d d->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.d d->lu
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endcase
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endcase
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//coverage off
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// turning coverage off here because rv64gc configuration does not support floating point halfs and quads
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// verified that these branches will not ever be taken in rv64gc configuration.
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7'b1101010: case(Rs2D)
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7'b1101010: case(Rs2D)
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h
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5'b00000: ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0; // fcvt.h.w w->h
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h
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5'b00001: ControlsD = `FCTRLW'b1_0_01_00_100_0_0_0; // fcvt.h.wu wu->h
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@ -203,12 +197,11 @@ module fctrl (
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5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu
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5'b00001: ControlsD = `FCTRLW'b0_1_01_00_000_0_0_1; // fcvt.wu.q q->wu
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1; // fcvt.l.q q->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1; // fcvt.lu.q q->lu
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endcase
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endcase
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// coverage on
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endcase
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endcase
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endcase
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endcase
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/* verilator lint_off CASEINCOMPLETE */
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end
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end
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/* verilator lint_on CASEINCOMPLETE */
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// unswizzle control bits
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// unswizzle control bits
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assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD;
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assign #1 {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, FDivStartD, IllegalFPUInstrD, FCvtIntD} = ControlsD;
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@ -334,7 +327,5 @@ module fctrl (
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flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW,
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flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW,
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{FRegWriteM, FResSelM, FCvtIntM},
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{FRegWriteM, FResSelM, FCvtIntM},
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{FRegWriteW, FResSelW, FCvtIntW});
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{FRegWriteW, FResSelW, FCvtIntW});
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//assign FCvtIntW = (FResSelW == 2'b01);
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endmodule
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endmodule
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@ -37,7 +37,7 @@ module alu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // For BMU decoding
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input logic [2:0] Funct3, // For BMU decoding
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input logic [1:0] CompFlags, // Comparator flags
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input logic CompLT, // Less-Than flag from comparator
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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output logic [WIDTH-1:0] Sum); // Sum of operands
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@ -90,7 +90,7 @@ module alu #(parameter WIDTH=32) (
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// Final Result B instruction select mux
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// Final Result B instruction select mux
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
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.Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult,
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.Funct3, .CompLT, .BALUControl, .ALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .Result);
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.CondMaskB, .CondShiftA, .Result);
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end else begin
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end else begin
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assign Result = ALUResult;
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assign Result = ALUResult;
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@ -35,7 +35,7 @@ module bitmanipalu #(parameter WIDTH=32) (
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
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input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
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input logic [1:0] CompFlags, // Comparator flags
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input logic CompLT, // Less-Than flag from comparator
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
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input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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@ -84,7 +84,7 @@ module bitmanipalu #(parameter WIDTH=32) (
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// ZBB Unit
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// ZBB Unit
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if (`ZBB_SUPPORTED) begin: zbb
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult);
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .W64, .lt(CompLT), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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end else assign ZBBResult = 0;
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// Result Select Mux
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// Result Select Mux
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@ -32,7 +32,7 @@
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module cnt #(parameter WIDTH = 32) (
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module cnt #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, RevA, // Operands
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input logic [WIDTH-1:0] A, RevA, // Operands
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input logic [4:0] B, // Last 5 bits of immediate
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input logic [1:0] B, // Last 2 bits of immediate
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input logic W64, // Indicates word operation
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input logic W64, // Indicates word operation
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output logic [WIDTH-1:0] CntResult // count result
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output logic [WIDTH-1:0] CntResult // count result
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);
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);
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@ -32,18 +32,17 @@
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module zbb #(parameter WIDTH=32) (
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module zbb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, RevA, B, // Operands
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input logic [WIDTH-1:0] A, RevA, B, // Operands
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input logic [WIDTH-1:0] ALUResult, // ALU Result
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input logic W64, // Indicates word operation
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input logic W64, // Indicates word operation
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input logic lt, // lt flag
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input logic lt, // lt flag
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input logic [2:0] ZBBSelect, // Indicates word operation
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input logic [2:0] ZBBSelect, // ZBB Result select signal
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output logic [WIDTH-1:0] ZBBResult); // ZBB result
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output logic [WIDTH-1:0] ZBBResult); // ZBB result
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logic [WIDTH-1:0] CntResult; // count result
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logic [WIDTH-1:0] CntResult; // count result
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logic [WIDTH-1:0] MinMaxResult; // min,max result
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logic [WIDTH-1:0] MinMaxResult; // min, max result
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logic [WIDTH-1:0] ByteResult; // byte results
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logic [WIDTH-1:0] ByteResult; // byte results
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logic [WIDTH-1:0] ExtResult; // sign/zero extend results
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logic [WIDTH-1:0] ExtResult; // sign/zero extend results
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult);
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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@ -114,7 +114,7 @@ module datapath (
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
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comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
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mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE);
|
alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE[0], BALUControlE, ALUResultE, IEUAdrE);
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mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
|
mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
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mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
|
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
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|
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@ -106,6 +106,7 @@ module csr #(parameter
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logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
|
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
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logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
|
logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM;
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logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
|
logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
|
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|
logic UngatedCSRMWriteM;
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logic WriteFRMM, WriteFFLAGSM;
|
logic WriteFRMM, WriteFFLAGSM;
|
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logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
|
logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM;
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logic [4:0] NextCauseM;
|
logic [4:0] NextCauseM;
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@ -199,9 +200,10 @@ module csr #(parameter
|
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assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
|
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
|
||||||
assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]};
|
assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[`XLEN-1], CSRWriteValM[3:0]};
|
||||||
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
|
||||||
assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
|
assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
|
||||||
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
|
assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
|
||||||
assign CSRUWriteM = CSRWriteM;
|
assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
|
||||||
|
assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM;
|
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assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
|
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
|
||||||
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
|
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
|
||||||
|
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@ -209,7 +211,7 @@ module csr #(parameter
|
|||||||
// CSRs
|
// CSRs
|
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///////////////////////////////////////////
|
///////////////////////////////////////////
|
||||||
|
|
||||||
csri csri(.clk, .reset, .InstrValidNotFlushedM,
|
csri csri(.clk, .reset,
|
||||||
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
|
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
|
||||||
.MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
|
.MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
|
||||||
.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
|
.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
|
||||||
@ -223,8 +225,8 @@ module csr #(parameter
|
|||||||
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
|
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
|
||||||
.STATUS_FS, .BigEndianM);
|
.STATUS_FS, .BigEndianM);
|
||||||
|
|
||||||
csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
|
csrm csrm(.clk, .reset,
|
||||||
.CSRMWriteM, .MTrapM, .CSRAdrM,
|
.UngatedCSRMWriteM, .CSRMWriteM, .MTrapM, .CSRAdrM,
|
||||||
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
|
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
|
||||||
.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
|
.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
|
||||||
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
|
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
|
||||||
@ -234,7 +236,7 @@ module csr #(parameter
|
|||||||
|
|
||||||
|
|
||||||
if (`S_SUPPORTED) begin:csrs
|
if (`S_SUPPORTED) begin:csrs
|
||||||
csrs csrs(.clk, .reset, .InstrValidNotFlushedM,
|
csrs csrs(.clk, .reset,
|
||||||
.CSRSWriteM, .STrapM, .CSRAdrM,
|
.CSRSWriteM, .STrapM, .CSRAdrM,
|
||||||
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
|
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
|
||||||
.STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
|
.STATUS_TVM, .MCOUNTEREN_TM(MCOUNTEREN_REGW[1]),
|
||||||
|
@ -35,7 +35,6 @@ module csri #(parameter
|
|||||||
SIE = 12'h104,
|
SIE = 12'h104,
|
||||||
SIP = 12'h144) (
|
SIP = 12'h144) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic InstrValidNotFlushedM,
|
|
||||||
input logic CSRMWriteM, CSRSWriteM,
|
input logic CSRMWriteM, CSRSWriteM,
|
||||||
input logic [`XLEN-1:0] CSRWriteValM,
|
input logic [`XLEN-1:0] CSRWriteValM,
|
||||||
input logic [11:0] CSRAdrM,
|
input logic [11:0] CSRAdrM,
|
||||||
@ -50,10 +49,10 @@ module csri #(parameter
|
|||||||
logic STIP;
|
logic STIP;
|
||||||
|
|
||||||
// Interrupt Write Enables
|
// Interrupt Write Enables
|
||||||
assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM;
|
assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP);
|
||||||
assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM;
|
assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE);
|
||||||
assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM;
|
assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP);
|
||||||
assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM;
|
assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE);
|
||||||
|
|
||||||
// Interrupt Pending and Enable Registers
|
// Interrupt Pending and Enable Registers
|
||||||
// MEIP, MTIP, MSIP are read-only
|
// MEIP, MTIP, MSIP are read-only
|
||||||
|
@ -73,8 +73,7 @@ module csrm #(parameter
|
|||||||
MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
|
MIDELEG_MASK = 12'h222 // we choose to not make machine interrupts delegable
|
||||||
) (
|
) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic InstrValidNotFlushedM,
|
input logic UngatedCSRMWriteM, CSRMWriteM, MTrapM,
|
||||||
input logic CSRMWriteM, MTrapM,
|
|
||||||
input logic [11:0] CSRAdrM,
|
input logic [11:0] CSRAdrM,
|
||||||
input logic [`XLEN-1:0] NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
|
input logic [`XLEN-1:0] NextEPCM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
|
||||||
input logic [4:0] NextCauseM,
|
input logic [4:0] NextCauseM,
|
||||||
@ -92,8 +91,7 @@ module csrm #(parameter
|
|||||||
);
|
);
|
||||||
|
|
||||||
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
|
||||||
logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW;
|
logic [`XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW;
|
||||||
logic [4:0] MCAUSE_REGW;
|
|
||||||
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
|
logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
|
||||||
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
|
logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
|
||||||
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
|
logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
|
||||||
@ -113,13 +111,13 @@ module csrm #(parameter
|
|||||||
else
|
else
|
||||||
assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
|
assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
|
||||||
|
|
||||||
assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i];
|
assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~ADDRLocked[i];
|
||||||
flopenr #(`PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[`PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]);
|
flopenr #(`PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[`PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]);
|
||||||
if (`XLEN==64) begin
|
if (`XLEN==64) begin
|
||||||
assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i];
|
assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~CFGLocked[i];
|
||||||
flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
|
flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
|
||||||
end else begin
|
end else begin
|
||||||
assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & InstrValidNotFlushedM & ~CFGLocked[i];
|
assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~CFGLocked[i];
|
||||||
flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
|
flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -134,19 +132,19 @@ module csrm #(parameter
|
|||||||
assign MHARTID_REGW = 0;
|
assign MHARTID_REGW = 0;
|
||||||
|
|
||||||
// Write machine Mode CSRs
|
// Write machine Mode CSRs
|
||||||
assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM;
|
assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS);
|
||||||
assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH) & InstrValidNotFlushedM & (`XLEN==32);
|
assign WriteMSTATUSHM = CSRMWriteM & (CSRAdrM == MSTATUSH)& (`XLEN==32);
|
||||||
assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM;
|
assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC);
|
||||||
assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM;
|
assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG);
|
||||||
assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM;
|
assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG);
|
||||||
assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & InstrValidNotFlushedM;
|
assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH);
|
||||||
assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & InstrValidNotFlushedM;
|
assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC));
|
||||||
assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & InstrValidNotFlushedM;
|
assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE));
|
||||||
assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & InstrValidNotFlushedM;
|
assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL));
|
||||||
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & InstrValidNotFlushedM;
|
assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN);
|
||||||
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & InstrValidNotFlushedM;
|
assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT);
|
||||||
|
|
||||||
assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
|
assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
|
||||||
|
|
||||||
// CSRs
|
// CSRs
|
||||||
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
|
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
|
||||||
@ -157,7 +155,7 @@ module csrm #(parameter
|
|||||||
|
|
||||||
flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
|
flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
|
||||||
flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
|
flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
|
||||||
flopenr #(5) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
|
flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW);
|
||||||
if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration
|
if(`QEMU) assign MTVAL_REGW = `XLEN'b0; // MTVAL tied to 0 in QEMU configuration
|
||||||
else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
|
else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
|
||||||
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
|
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
|
||||||
@ -199,7 +197,7 @@ module csrm #(parameter
|
|||||||
MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
|
MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
|
||||||
MSCRATCH: CSRMReadValM = MSCRATCH_REGW;
|
MSCRATCH: CSRMReadValM = MSCRATCH_REGW;
|
||||||
MEPC: CSRMReadValM = MEPC_REGW;
|
MEPC: CSRMReadValM = MEPC_REGW;
|
||||||
MCAUSE: CSRMReadValM = {MCAUSE_REGW[4], {(`XLEN-5){1'b0}}, MCAUSE_REGW[3:0]};
|
MCAUSE: CSRMReadValM = MCAUSE_REGW;
|
||||||
MTVAL: CSRMReadValM = MTVAL_REGW;
|
MTVAL: CSRMReadValM = MTVAL_REGW;
|
||||||
MTINST: CSRMReadValM = 0; // implemented as trivial zero
|
MTINST: CSRMReadValM = 0; // implemented as trivial zero
|
||||||
MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
|
MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
|
||||||
|
@ -45,7 +45,6 @@ module csrs #(parameter
|
|||||||
STIMECMPH = 12'h15D,
|
STIMECMPH = 12'h15D,
|
||||||
SATP = 12'h180) (
|
SATP = 12'h180) (
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic InstrValidNotFlushedM,
|
|
||||||
input logic CSRSWriteM, STrapM,
|
input logic CSRSWriteM, STrapM,
|
||||||
input logic [11:0] CSRAdrM,
|
input logic [11:0] CSRAdrM,
|
||||||
input logic [`XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW,
|
input logic [`XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW,
|
||||||
@ -73,28 +72,26 @@ module csrs #(parameter
|
|||||||
logic WriteSSCRATCHM, WriteSEPCM;
|
logic WriteSSCRATCHM, WriteSEPCM;
|
||||||
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
|
logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
|
||||||
logic WriteSTIMECMPM, WriteSTIMECMPHM;
|
logic WriteSTIMECMPM, WriteSTIMECMPHM;
|
||||||
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
|
logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
|
||||||
logic [4:0] SCAUSE_REGW;
|
|
||||||
logic [63:0] STIMECMP_REGW;
|
logic [63:0] STIMECMP_REGW;
|
||||||
|
|
||||||
// write enables
|
// write enables
|
||||||
// *** can InstrValidNotFlushed be factored out of all these writes into CSRWriteM?
|
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS);
|
||||||
assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
|
assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC);
|
||||||
assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
|
assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH);
|
||||||
assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
|
assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC));
|
||||||
assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM;
|
assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE));
|
||||||
assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM;
|
assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
|
||||||
assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM;
|
assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM);
|
||||||
assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM;
|
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
|
||||||
assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM;
|
assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM);
|
||||||
assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & InstrValidNotFlushedM;
|
assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & (`XLEN == 32);
|
||||||
assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == `M_MODE | MCOUNTEREN_TM) & (`XLEN == 32) & InstrValidNotFlushedM;
|
|
||||||
|
|
||||||
// CSRs
|
// CSRs
|
||||||
flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW);
|
flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW);
|
||||||
flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
|
flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
|
||||||
flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
|
flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
|
||||||
flopenr #(5) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW);
|
flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(`XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW);
|
||||||
flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
|
flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
|
||||||
if (`VIRTMEM_SUPPORTED)
|
if (`VIRTMEM_SUPPORTED)
|
||||||
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
|
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
|
||||||
@ -127,7 +124,7 @@ module csrs #(parameter
|
|||||||
SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields
|
SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields
|
||||||
SSCRATCH: CSRSReadValM = SSCRATCH_REGW;
|
SSCRATCH: CSRSReadValM = SSCRATCH_REGW;
|
||||||
SEPC: CSRSReadValM = SEPC_REGW;
|
SEPC: CSRSReadValM = SEPC_REGW;
|
||||||
SCAUSE: CSRSReadValM = {SCAUSE_REGW[4], {(`XLEN-5){1'b0}}, SCAUSE_REGW[3:0]};
|
SCAUSE: CSRSReadValM = SCAUSE_REGW;
|
||||||
STVAL: CSRSReadValM = STVAL_REGW;
|
STVAL: CSRSReadValM = STVAL_REGW;
|
||||||
SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
|
SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
|
||||||
else begin
|
else begin
|
||||||
|
@ -51,9 +51,8 @@ module csru #(parameter
|
|||||||
logic SetOrWriteFFLAGSM;
|
logic SetOrWriteFFLAGSM;
|
||||||
|
|
||||||
// Write enables
|
// Write enables
|
||||||
//assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM;
|
assign WriteFRMM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
|
||||||
assign WriteFRMM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM;
|
assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR);
|
||||||
assign WriteFFLAGSM = (CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM;
|
|
||||||
|
|
||||||
// Write Values
|
// Write Values
|
||||||
assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
|
assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
|
||||||
|
@ -1,7 +1,8 @@
|
|||||||
///////////////////////////////////////////
|
<///////////////////////////////////////////
|
||||||
//
|
//
|
||||||
// Written: me@KatherineParry.com
|
// Written: me@KatherineParry.com
|
||||||
// Modified: 7/5/2022
|
// Modified: 7/5/2022
|
||||||
|
// Modified: 4/2/2023
|
||||||
//
|
//
|
||||||
// Purpose: Testbench for Testfloat
|
// Purpose: Testbench for Testfloat
|
||||||
//
|
//
|
||||||
@ -32,75 +33,74 @@
|
|||||||
module testbenchfp;
|
module testbenchfp;
|
||||||
parameter TEST="none";
|
parameter TEST="none";
|
||||||
|
|
||||||
string Tests[]; // list of tests to be run
|
string Tests[]; // list of tests to be run
|
||||||
logic [2:0] OpCtrl[]; // list of op controls
|
logic [2:0] OpCtrl[]; // list of op controls
|
||||||
logic [2:0] Unit[]; // list of units being tested
|
logic [2:0] Unit[]; // list of units being tested
|
||||||
logic WriteInt[]; // Is being written to integer resgiter
|
logic WriteInt[]; // Is being written to integer resgiter
|
||||||
logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
|
logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
|
||||||
logic [1:0] Fmt[]; // list of formats for the other units
|
logic [1:0] Fmt[]; // list of formats for the other units
|
||||||
|
|
||||||
|
|
||||||
logic clk=0;
|
logic clk=0;
|
||||||
logic [31:0] TestNum=0; // index for the test
|
logic [31:0] TestNum=0; // index for the test
|
||||||
logic [31:0] OpCtrlNum=0; // index for OpCtrl
|
logic [31:0] OpCtrlNum=0; // index for OpCtrl
|
||||||
logic [31:0] errors=0; // how many errors
|
logic [31:0] errors=0; // how many errors
|
||||||
logic [31:0] VectorNum=0; // index for test vector
|
logic [31:0] VectorNum=0; // index for test vector
|
||||||
logic [31:0] FrmNum=0; // index for rounding mode
|
logic [31:0] FrmNum=0; // index for rounding mode
|
||||||
logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
|
logic [`FLEN*4+7:0] TestVectors[8388609:0]; // list of test vectors
|
||||||
|
|
||||||
logic [1:0] FmtVal; // value of the current Fmt
|
logic [1:0] FmtVal; // value of the current Fmt
|
||||||
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
|
logic [2:0] UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
|
||||||
logic WriteIntVal; // value of the current WriteInt
|
logic WriteIntVal; // value of the current WriteInt
|
||||||
logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
|
logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat
|
||||||
logic [`XLEN-1:0] SrcA; // integer input
|
logic [`XLEN-1:0] SrcA; // integer input
|
||||||
logic [`FLEN-1:0] Ans; // correct answer from TestFloat
|
logic [`FLEN-1:0] Ans; // correct answer from TestFloat
|
||||||
logic [`FLEN-1:0] Res; // result from other units
|
logic [`FLEN-1:0] Res; // result from other units
|
||||||
logic [4:0] AnsFlg; // correct flags read from testfloat
|
logic [4:0] AnsFlg; // correct flags read from testfloat
|
||||||
logic [4:0] ResFlg, Flg; // Result flags
|
logic [4:0] ResFlg, Flg; // Result flags
|
||||||
logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
|
||||||
logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
|
logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
|
||||||
logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
|
logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit
|
||||||
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
|
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
|
||||||
logic AnsNaN, ResNaN, NaNGood;
|
logic AnsNaN, ResNaN, NaNGood;
|
||||||
logic Xs, Ys, Zs; // sign of the inputs
|
logic Xs, Ys, Zs; // sign of the inputs
|
||||||
logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
|
logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs
|
||||||
logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
|
logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs
|
||||||
logic XNaN, YNaN, ZNaN; // is the input NaN
|
logic XNaN, YNaN, ZNaN; // is the input NaN
|
||||||
logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
|
logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN
|
||||||
logic XSubnorm, ZSubnorm; // is the input denormalized
|
logic XSubnorm, ZSubnorm; // is the input denormalized
|
||||||
logic XInf, YInf, ZInf; // is the input infinity
|
logic XInf, YInf, ZInf; // is the input infinity
|
||||||
logic XZero, YZero, ZZero; // is the input zero
|
logic XZero, YZero, ZZero; // is the input zero
|
||||||
logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
|
logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones
|
||||||
logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
|
logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder)
|
||||||
logic IntZero;
|
logic IntZero;
|
||||||
logic CvtResSgnE;
|
logic CvtResSgnE;
|
||||||
logic [`NE:0] CvtCalcExpE; // the calculated expoent
|
logic [`NE:0] CvtCalcExpE; // the calculated expoent
|
||||||
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
|
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
|
||||||
logic [`DIVb:0] Quot;
|
logic [`DIVb:0] Quot;
|
||||||
logic CvtResSubnormUfE;
|
logic CvtResSubnormUfE;
|
||||||
logic DivStart, FDivBusyE, OldFDivBusyE;
|
logic DivStart, FDivBusyE, OldFDivBusyE;
|
||||||
logic reset = 1'b0;
|
logic reset = 1'b0;
|
||||||
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
|
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
|
||||||
logic [`DURLEN-1:0] Dur;
|
logic [`DURLEN-1:0] Dur;
|
||||||
|
|
||||||
// in-between FMA signals
|
// in-between FMA signals
|
||||||
logic Mult;
|
logic Mult;
|
||||||
logic Ss;
|
logic Ss;
|
||||||
logic [`NE+1:0] Pe;
|
logic [`NE+1:0] Pe;
|
||||||
logic [`NE+1:0] Se;
|
logic [`NE+1:0] Se;
|
||||||
logic ASticky;
|
logic ASticky;
|
||||||
logic KillProd;
|
logic KillProd;
|
||||||
logic [$clog2(3*`NF+5)-1:0] SCnt;
|
logic [$clog2(3*`NF+5)-1:0] SCnt;
|
||||||
logic [3*`NF+3:0] Sm;
|
logic [3*`NF+3:0] Sm;
|
||||||
logic InvA;
|
logic InvA;
|
||||||
logic NegSum;
|
logic NegSum;
|
||||||
logic As;
|
logic As;
|
||||||
logic Ps;
|
logic Ps;
|
||||||
logic DivSticky;
|
logic DivSticky;
|
||||||
logic DivDone;
|
logic DivDone;
|
||||||
logic DivNegSticky;
|
logic DivNegSticky;
|
||||||
logic [`NE+1:0] DivCalcExp;
|
logic [`NE+1:0] DivCalcExp;
|
||||||
logic divsqrtop;
|
logic divsqrtop;
|
||||||
|
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
@ -126,28 +126,28 @@ module testbenchfp;
|
|||||||
$display("TEST is %s", TEST);
|
$display("TEST is %s", TEST);
|
||||||
if (`Q_SUPPORTED) begin // if Quad percision is supported
|
if (`Q_SUPPORTED) begin // if Quad percision is supported
|
||||||
if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion
|
if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion
|
||||||
// add the 128-bit cvtint tests to the to-be-tested list
|
// add the 128-bit cvtint tests to the to-be-tested list
|
||||||
Tests = {Tests, f128rv32cvtint};
|
Tests = {Tests, f128rv32cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b11};
|
Fmt = {Fmt, 2'b11};
|
||||||
end
|
end
|
||||||
if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
|
if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions
|
||||||
Tests = {Tests, f128rv64cvtint};
|
Tests = {Tests, f128rv64cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b11};
|
Fmt = {Fmt, 2'b11};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested
|
if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested
|
||||||
if(`D_SUPPORTED) begin // if double precision is supported
|
if(`D_SUPPORTED) begin // if double precision is supported
|
||||||
// add the 128 <-> 64 bit conversions to the to-be-tested list
|
// add the 128 <-> 64 bit conversions to the to-be-tested list
|
||||||
@ -270,27 +270,27 @@ module testbenchfp;
|
|||||||
end
|
end
|
||||||
if (`D_SUPPORTED) begin // if double precision is supported
|
if (`D_SUPPORTED) begin // if double precision is supported
|
||||||
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
|
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
|
||||||
Tests = {Tests, f64rv32cvtint};
|
Tests = {Tests, f64rv32cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b01};
|
Fmt = {Fmt, 2'b01};
|
||||||
end
|
end
|
||||||
if (`XLEN == 64) begin // if 64-bit integers are being supported
|
if (`XLEN == 64) begin // if 64-bit integers are being supported
|
||||||
Tests = {Tests, f64rv64cvtint};
|
Tests = {Tests, f64rv64cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b01};
|
Fmt = {Fmt, 2'b01};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
|
if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested
|
||||||
if(`F_SUPPORTED) begin // if single precision is supported
|
if(`F_SUPPORTED) begin // if single precision is supported
|
||||||
// add the 64 <-> 32 bit conversions to the to-be-tested list
|
// add the 64 <-> 32 bit conversions to the to-be-tested list
|
||||||
@ -397,27 +397,27 @@ module testbenchfp;
|
|||||||
end
|
end
|
||||||
if (`F_SUPPORTED) begin // if single precision being supported
|
if (`F_SUPPORTED) begin // if single precision being supported
|
||||||
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
|
if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested
|
||||||
Tests = {Tests, f32rv32cvtint};
|
Tests = {Tests, f32rv32cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b00};
|
Fmt = {Fmt, 2'b00};
|
||||||
end
|
end
|
||||||
if (`XLEN == 64) begin // if 64-bit integers are supported
|
if (`XLEN == 64) begin // if 64-bit integers are supported
|
||||||
Tests = {Tests, f32rv64cvtint};
|
Tests = {Tests, f32rv64cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b00};
|
Fmt = {Fmt, 2'b00};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested
|
if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested
|
||||||
if(`ZFH_SUPPORTED) begin
|
if(`ZFH_SUPPORTED) begin
|
||||||
// add the 32 <-> 16 bit conversions to the to-be-tested list
|
// add the 32 <-> 16 bit conversions to the to-be-tested list
|
||||||
@ -508,27 +508,27 @@ module testbenchfp;
|
|||||||
end
|
end
|
||||||
if (`ZFH_SUPPORTED) begin // if half precision supported
|
if (`ZFH_SUPPORTED) begin // if half precision supported
|
||||||
if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested
|
if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested
|
||||||
Tests = {Tests, f16rv32cvtint};
|
Tests = {Tests, f16rv32cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b10};
|
Fmt = {Fmt, 2'b10};
|
||||||
end
|
end
|
||||||
if (`XLEN == 64) begin // if 64-bit integers are supported
|
if (`XLEN == 64) begin // if 64-bit integers are supported
|
||||||
Tests = {Tests, f16rv64cvtint};
|
Tests = {Tests, f16rv64cvtint};
|
||||||
// add the op-codes for these tests to the op-code list
|
// add the op-codes for these tests to the op-code list
|
||||||
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL};
|
||||||
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1};
|
||||||
// add what unit is used and the fmt to their lists (one for each test)
|
// add what unit is used and the fmt to their lists (one for each test)
|
||||||
for(int i = 0; i<20; i++) begin
|
for(int i = 0; i<20; i++) begin
|
||||||
Unit = {Unit, `CVTINTUNIT};
|
Unit = {Unit, `CVTINTUNIT};
|
||||||
Fmt = {Fmt, 2'b10};
|
Fmt = {Fmt, 2'b10};
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
|
if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested
|
||||||
// add the correct tests/op-ctrls/unit/fmt to their lists
|
// add the correct tests/op-ctrls/unit/fmt to their lists
|
||||||
Tests = {Tests, f16cmp};
|
Tests = {Tests, f16cmp};
|
||||||
@ -656,7 +656,8 @@ module testbenchfp;
|
|||||||
end
|
end
|
||||||
|
|
||||||
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
|
// extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
|
||||||
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
|
readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]),
|
||||||
|
.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
|
||||||
.Xs, .Ys, .Zs, .Unit(UnitVal),
|
.Xs, .Ys, .Zs, .Unit(UnitVal),
|
||||||
.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
|
.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
|
||||||
.Xm, .Ym, .Zm, .DivStart,
|
.Xm, .Ym, .Zm, .DivStart,
|
||||||
@ -680,7 +681,7 @@ module testbenchfp;
|
|||||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
// instantiate devices under test
|
// instantiate devices under test
|
||||||
if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "all") begin : fma
|
if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma
|
||||||
fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs),
|
fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs),
|
||||||
.Xe(Xe), .Ye(Ye), .Ze(Ze),
|
.Xe(Xe), .Ye(Ye), .Ze(Ze),
|
||||||
.Xm(Xm), .Ym(Ym), .Zm(Zm),
|
.Xm(Xm), .Ym(Ym), .Zm(Zm),
|
||||||
@ -1331,4 +1332,4 @@ module readvectors (
|
|||||||
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
|
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
|
||||||
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
|
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
|
||||||
.XEn, .YEn, .ZEn, .XExpMax);
|
.XEn, .YEn, .ZEn, .XExpMax);
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
|
|
||||||
main:
|
main:
|
||||||
|
|
||||||
bseti t0, zero, 14 # turn on FPU
|
#bseti t0, zero, 14 # turn on FPU
|
||||||
csrs mstatus, t0
|
csrs mstatus, t0
|
||||||
|
|
||||||
# Test legal instructions not covered elsewhere
|
# Test legal instructions not covered elsewhere
|
||||||
@ -36,6 +36,8 @@ main:
|
|||||||
flh ft0, 8(a0)
|
flh ft0, 8(a0)
|
||||||
fsq ft0, 0(a0)
|
fsq ft0, 0(a0)
|
||||||
fsh ft0, 8(a0)
|
fsh ft0, 8(a0)
|
||||||
|
|
||||||
|
# Tests for fpu/fctrl.sv
|
||||||
fcvt.h.s ft1, ft0
|
fcvt.h.s ft1, ft0
|
||||||
fcvt.q.s ft2, ft0
|
fcvt.q.s ft2, ft0
|
||||||
fcvt.h.w ft3, a0
|
fcvt.h.w ft3, a0
|
||||||
@ -55,6 +57,7 @@ main:
|
|||||||
fcvt.l.q a0, ft3
|
fcvt.l.q a0, ft3
|
||||||
fcvt.lu.q a0, ft3
|
fcvt.lu.q a0, ft3
|
||||||
|
|
||||||
|
<<<<<<< HEAD
|
||||||
|
|
||||||
// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
|
// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
|
||||||
# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
|
# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
|
||||||
@ -72,6 +75,8 @@ main:
|
|||||||
.word 0xd2400053 // Line 168 All False Test case - illegal instruction?
|
.word 0xd2400053 // Line 168 All False Test case - illegal instruction?
|
||||||
.word 0xc2400053 // Line 174 All False Test case - illegal instruction?
|
.word 0xc2400053 // Line 174 All False Test case - illegal instruction?
|
||||||
|
|
||||||
|
=======
|
||||||
|
>>>>>>> d4b7da34dee55ec8394ab391ecd6514c887a9790
|
||||||
# Test illegal instructions are detected
|
# Test illegal instructions are detected
|
||||||
.word 0x00000007 // illegal floating-point load (bad Funct3)
|
.word 0x00000007 // illegal floating-point load (bad Funct3)
|
||||||
.word 0x00000027 // illegal floating-point store (bad Funct3)
|
.word 0x00000027 // illegal floating-point store (bad Funct3)
|
||||||
|
@ -36,4 +36,11 @@ main:
|
|||||||
addi t0, zero, 0
|
addi t0, zero, 0
|
||||||
csrr t0, stimecmp
|
csrr t0, stimecmp
|
||||||
|
|
||||||
|
# Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
|
||||||
|
li t0, 0
|
||||||
|
csrw stval, t0
|
||||||
|
csrw scause, t0
|
||||||
|
csrw sepc, t0
|
||||||
|
csrw stimecmp, t0
|
||||||
|
|
||||||
j done
|
j done
|
||||||
|
4
tests/fp/combined_IF_vectors/IF_vectors/README
Normal file
4
tests/fp/combined_IF_vectors/IF_vectors/README
Normal file
@ -0,0 +1,4 @@
|
|||||||
|
This folder holds the archtest and testfloat vectors necessary fo evaluating performance
|
||||||
|
of standalone intdiv vs combined IFdivsqrt
|
||||||
|
|
||||||
|
to generate vectors, uncomment line 8 in create_all_vectors.sh
|
8
tests/fp/combined_IF_vectors/create_IF_vectors.sh
Executable file
8
tests/fp/combined_IF_vectors/create_IF_vectors.sh
Executable file
@ -0,0 +1,8 @@
|
|||||||
|
#!/bin/sh
|
||||||
|
# create test vectors for stand alone int
|
||||||
|
|
||||||
|
./extract_testfloat_vectors.py
|
||||||
|
./extract_arch_vectors.py
|
||||||
|
|
||||||
|
# to create tvs for evaluation of combined IFdivsqrt
|
||||||
|
#./combined_IF_vectors/create_IF_vectors.sh
|
251
tests/fp/combined_IF_vectors/extract_arch_vectors.py
Executable file
251
tests/fp/combined_IF_vectors/extract_arch_vectors.py
Executable file
@ -0,0 +1,251 @@
|
|||||||
|
#! /usr/bin/python3
|
||||||
|
|
||||||
|
# author: Alessandro Maiuolo
|
||||||
|
# contact: amaiuolo@g.hmc.edu
|
||||||
|
# date created: 3-29-2023
|
||||||
|
|
||||||
|
# extract all arch test vectors
|
||||||
|
import os
|
||||||
|
wally = os.popen('echo $WALLY').read().strip()
|
||||||
|
|
||||||
|
def ext_bits(my_string):
|
||||||
|
target_len = 32 # we want 128 bits, div by 4 bc hex notation
|
||||||
|
zeroes_to_add = target_len - len(my_string)
|
||||||
|
return zeroes_to_add*"0" + my_string
|
||||||
|
|
||||||
|
def twos_comp(b, x):
|
||||||
|
if b == 32:
|
||||||
|
return hex(0x100000000 - int(x,16))[2:]
|
||||||
|
elif b == 64:
|
||||||
|
return hex(0x10000000000000000 - int(x,16))[2:]
|
||||||
|
else:
|
||||||
|
return "UNEXPECTED_BITSIZE"
|
||||||
|
|
||||||
|
def unpack_rf(packed):
|
||||||
|
bin_u = bin(int(packed, 16))[2:].zfill(8) # translate to binary
|
||||||
|
flags = hex(int(bin_u[3:],2))[2:].zfill(2)
|
||||||
|
rounding_mode = hex(int(bin_u[:3],2))[2:]
|
||||||
|
return flags, rounding_mode
|
||||||
|
|
||||||
|
# rounding mode dictionary
|
||||||
|
round_dict = {
|
||||||
|
"rne":"0",
|
||||||
|
"rnm":"4",
|
||||||
|
"ru":"3",
|
||||||
|
"rz":"1",
|
||||||
|
"rd":"2",
|
||||||
|
"dyn":"7"
|
||||||
|
}
|
||||||
|
|
||||||
|
# fcsr dictionary
|
||||||
|
fcsr_dict = {
|
||||||
|
"0":"rne",
|
||||||
|
"128":"rnm",
|
||||||
|
"96":"ru",
|
||||||
|
"32":"rz",
|
||||||
|
"64":"rd",
|
||||||
|
"224":"dyn"
|
||||||
|
}
|
||||||
|
|
||||||
|
print("creating arch test vectors")
|
||||||
|
|
||||||
|
class Config:
|
||||||
|
def __init__(self, bits, letter, op, filt, op_code):
|
||||||
|
self.bits = bits
|
||||||
|
self.letter = letter
|
||||||
|
self.op = op
|
||||||
|
self.filt = filt
|
||||||
|
self.op_code = op_code
|
||||||
|
|
||||||
|
def create_vectors(my_config):
|
||||||
|
suite_folder_num = my_config.bits
|
||||||
|
if my_config.bits == 64 and my_config.letter == "F": suite_folder_num = 32
|
||||||
|
source_dir1 = "{}/addins/riscv-arch-test/riscv-test-suite/rv{}i_m/{}/src/".format(wally, suite_folder_num, my_config.letter)
|
||||||
|
source_dir2 = "{}/tests/riscof/work/riscv-arch-test/rv{}i_m/{}/src/".format(wally, my_config.bits, my_config.letter)
|
||||||
|
dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
|
||||||
|
all_vectors1 = os.listdir(source_dir1)
|
||||||
|
|
||||||
|
filt_vectors1 = [v for v in all_vectors1 if my_config.filt in v]
|
||||||
|
# print(filt_vectors1)
|
||||||
|
filt_vectors2 = [v + "/ref/Reference-sail_c_simulator.signature" for v in all_vectors1 if my_config.filt in v]
|
||||||
|
|
||||||
|
# iterate through all vectors
|
||||||
|
for i in range(len(filt_vectors1)):
|
||||||
|
vector1 = filt_vectors1[i]
|
||||||
|
vector2 = filt_vectors2[i]
|
||||||
|
operation = my_config.op_code
|
||||||
|
rounding_mode = "X"
|
||||||
|
flags = "XX"
|
||||||
|
# use name to create our new tv
|
||||||
|
dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
|
||||||
|
# open vectors
|
||||||
|
src_file1 = open(source_dir1 + vector1,'r')
|
||||||
|
src_file2 = open(source_dir2 + vector2,'r')
|
||||||
|
# for each test in the vector
|
||||||
|
reading = True
|
||||||
|
src_file2.readline() #skip first bc junk
|
||||||
|
# print(my_config.bits, my_config.letter)
|
||||||
|
if my_config.letter == "F" and my_config.bits == 64:
|
||||||
|
reading = True
|
||||||
|
# print("trigger 64F")
|
||||||
|
#skip first 2 lines bc junk
|
||||||
|
src_file2.readline()
|
||||||
|
while reading:
|
||||||
|
# get answer and flags from Ref...signature
|
||||||
|
# answers are before deadbeef (first line of 4)
|
||||||
|
# flags are after deadbeef (third line of 4)
|
||||||
|
answer = src_file2.readline().strip()
|
||||||
|
deadbeef = src_file2.readline().strip()
|
||||||
|
# print(answer)
|
||||||
|
if not (answer == "e7d4b281" and deadbeef == "6f5ca309"): # if there is still stuff to read
|
||||||
|
# get flags
|
||||||
|
packed = src_file2.readline().strip()[6:]
|
||||||
|
flags, rounding_mode = unpack_rf(packed)
|
||||||
|
# skip 00000000 buffer
|
||||||
|
src_file2.readline()
|
||||||
|
|
||||||
|
# parse through .S file
|
||||||
|
detected = False
|
||||||
|
done = False
|
||||||
|
op1val = "0"
|
||||||
|
op2val = "0"
|
||||||
|
while not (detected or done):
|
||||||
|
# print("det1")
|
||||||
|
line = src_file1.readline()
|
||||||
|
# print(line)
|
||||||
|
if "op1val" in line:
|
||||||
|
# print("det2")
|
||||||
|
# parse line
|
||||||
|
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||||
|
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||||
|
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||||
|
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||||
|
else:
|
||||||
|
op2val = 32*"X"
|
||||||
|
# go to next test in vector
|
||||||
|
detected = True
|
||||||
|
elif "RVTEST_CODE_END" in line:
|
||||||
|
done = True
|
||||||
|
# put it all together
|
||||||
|
if not done:
|
||||||
|
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags, rounding_mode)
|
||||||
|
dest_file.write(translation + "\n")
|
||||||
|
else:
|
||||||
|
# print("read false")
|
||||||
|
reading = False
|
||||||
|
elif my_config.letter == "M" and my_config.bits == 64:
|
||||||
|
reading = True
|
||||||
|
#skip first 2 lines bc junk
|
||||||
|
src_file2.readline()
|
||||||
|
while reading:
|
||||||
|
# print("trigger 64M")
|
||||||
|
# get answer from Ref...signature
|
||||||
|
# answers span two lines and are reversed
|
||||||
|
answer2 = src_file2.readline().strip()
|
||||||
|
answer1 = src_file2.readline().strip()
|
||||||
|
answer = answer1 + answer2
|
||||||
|
# print(answer1,answer2)
|
||||||
|
if not (answer2 == "e7d4b281" and answer1 == "6f5ca309"): # if there is still stuff to read
|
||||||
|
# parse through .S file
|
||||||
|
detected = False
|
||||||
|
done = False
|
||||||
|
op1val = "0"
|
||||||
|
op2val = "0"
|
||||||
|
while not (detected or done):
|
||||||
|
# print("det1")
|
||||||
|
line = src_file1.readline()
|
||||||
|
# print(line)
|
||||||
|
if "op1val" in line:
|
||||||
|
# print("det2")
|
||||||
|
# parse line
|
||||||
|
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||||
|
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||||
|
op1val = twos_comp(my_config.bits, op1val)
|
||||||
|
if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
|
||||||
|
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||||
|
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||||
|
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||||
|
op2val = twos_comp(my_config.bits, op2val)
|
||||||
|
# go to next test in vector
|
||||||
|
detected = True
|
||||||
|
elif "RVTEST_CODE_END" in line:
|
||||||
|
done = True
|
||||||
|
# ints don't have flags
|
||||||
|
flags = "XX"
|
||||||
|
# put it all together
|
||||||
|
if not done:
|
||||||
|
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
|
||||||
|
dest_file.write(translation + "\n")
|
||||||
|
else:
|
||||||
|
# print("read false")
|
||||||
|
reading = False
|
||||||
|
else:
|
||||||
|
while reading:
|
||||||
|
# get answer and flags from Ref...signature
|
||||||
|
answer = src_file2.readline()
|
||||||
|
# print(answer)
|
||||||
|
packed = src_file2.readline()[6:]
|
||||||
|
# print(packed)
|
||||||
|
if len(packed.strip())>0: # if there is still stuff to read
|
||||||
|
# print("packed")
|
||||||
|
# parse through .S file
|
||||||
|
detected = False
|
||||||
|
done = False
|
||||||
|
op1val = "0"
|
||||||
|
op2val = "0"
|
||||||
|
while not (detected or done):
|
||||||
|
# print("det1")
|
||||||
|
line = src_file1.readline()
|
||||||
|
# print(line)
|
||||||
|
if "op1val" in line:
|
||||||
|
# print("det2")
|
||||||
|
# parse line
|
||||||
|
op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
|
||||||
|
if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
|
||||||
|
op1val = twos_comp(my_config.bits, op1val)
|
||||||
|
if my_config.op != "fsqrt": # sqrt doesn't have two input vals
|
||||||
|
op2val = line.split("op2val")[1].split("x")[1].strip()
|
||||||
|
if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
|
||||||
|
if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
|
||||||
|
op2val = twos_comp(my_config.bits, op2val)
|
||||||
|
# go to next test in vector
|
||||||
|
detected = True
|
||||||
|
elif "RVTEST_CODE_END" in line:
|
||||||
|
done = True
|
||||||
|
# rounding mode for float
|
||||||
|
if not done and (my_config.op == "fsqrt" or my_config.op == "fdiv"):
|
||||||
|
flags, rounding_mode = unpack_rf(packed)
|
||||||
|
|
||||||
|
# put it all together
|
||||||
|
if not done:
|
||||||
|
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags, rounding_mode)
|
||||||
|
dest_file.write(translation + "\n")
|
||||||
|
else:
|
||||||
|
# print("read false")
|
||||||
|
reading = False
|
||||||
|
print("out")
|
||||||
|
dest_file.close()
|
||||||
|
src_file1.close()
|
||||||
|
src_file2.close()
|
||||||
|
|
||||||
|
config_list = [
|
||||||
|
Config(32, "M", "div", "div_", 0),
|
||||||
|
Config(32, "F", "fdiv", "fdiv", 1),
|
||||||
|
Config(32, "F", "fsqrt", "fsqrt", 2),
|
||||||
|
Config(32, "M", "rem", "rem-", 3),
|
||||||
|
Config(32, "M", "divu", "divu-", 4),
|
||||||
|
Config(32, "M", "remu", "remu-", 5),
|
||||||
|
Config(64, "M", "div", "div-", 0),
|
||||||
|
Config(64, "F", "fdiv", "fdiv", 1),
|
||||||
|
Config(64, "F", "fsqrt", "fsqrt", 2),
|
||||||
|
Config(64, "M", "rem", "rem-", 3),
|
||||||
|
Config(64, "M", "divu", "divu-", 4),
|
||||||
|
Config(64, "M", "remu", "remu-", 5),
|
||||||
|
Config(64, "M", "divw", "divw-", 6),
|
||||||
|
Config(64, "M", "divuw", "divuw-", 7),
|
||||||
|
Config(64, "M", "remw", "remw-", 8),
|
||||||
|
Config(64, "M", "remuw", "remuw-", 9)
|
||||||
|
]
|
||||||
|
|
||||||
|
for c in config_list:
|
||||||
|
create_vectors(c)
|
79
tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
Executable file
79
tests/fp/combined_IF_vectors/extract_testfloat_vectors.py
Executable file
@ -0,0 +1,79 @@
|
|||||||
|
#! /usr/bin/python3
|
||||||
|
# extract sqrt and float div testfloat vectors
|
||||||
|
|
||||||
|
# author: Alessandro Maiuolo
|
||||||
|
# contact: amaiuolo@g.hmc.edu
|
||||||
|
# date created: 3-29-2023
|
||||||
|
|
||||||
|
import os
|
||||||
|
wally = os.popen('echo $WALLY').read().strip()
|
||||||
|
# print(wally)
|
||||||
|
|
||||||
|
def ext_bits(my_string):
|
||||||
|
target_len = 32 # we want 128 bits, div by 4 bc hex notation
|
||||||
|
zeroes_to_add = target_len - len(my_string)
|
||||||
|
return zeroes_to_add*"0" + my_string
|
||||||
|
|
||||||
|
# rounding mode dictionary
|
||||||
|
round_dict = {
|
||||||
|
"rne":"0",
|
||||||
|
"rnm":"4",
|
||||||
|
"ru":"3",
|
||||||
|
"rz":"1",
|
||||||
|
"rd":"2",
|
||||||
|
"dyn":"7"
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
print("creating testfloat div test vectors")
|
||||||
|
|
||||||
|
source_dir = "{}/tests/fp/vectors/".format(wally)
|
||||||
|
dest_dir = "{}/tests/fp/combined_IF_vectors/IF_vectors/".format(wally)
|
||||||
|
all_vectors = os.listdir(source_dir)
|
||||||
|
|
||||||
|
div_vectors = [v for v in all_vectors if "div" in v]
|
||||||
|
|
||||||
|
# iterate through all float div vectors
|
||||||
|
for vector in div_vectors:
|
||||||
|
# use name to determine configs
|
||||||
|
config_list = vector.split(".")[0].split("_")
|
||||||
|
operation = "1" #float div
|
||||||
|
rounding_mode = round_dict[str(config_list[2])]
|
||||||
|
# use name to create our new tv
|
||||||
|
dest_file = open(dest_dir + "cvw_" + vector, 'a')
|
||||||
|
# open vector
|
||||||
|
src_file = open(source_dir + vector,'r')
|
||||||
|
# for each test in the vector
|
||||||
|
for i in src_file.readlines():
|
||||||
|
translation = "" # this stores the test that we are currently working on
|
||||||
|
[input_1, input_2, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||||
|
# put it all together, strip nec for removing \n on the end of the flags
|
||||||
|
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), ext_bits(input_2), ext_bits(answer), flags.strip(), rounding_mode)
|
||||||
|
dest_file.write(translation + "\n")
|
||||||
|
dest_file.close()
|
||||||
|
src_file.close()
|
||||||
|
|
||||||
|
|
||||||
|
print("creating testfloat sqrt test vectors")
|
||||||
|
|
||||||
|
sqrt_vectors = [v for v in all_vectors if "sqrt" in v]
|
||||||
|
|
||||||
|
# iterate through all float div vectors
|
||||||
|
for vector in sqrt_vectors:
|
||||||
|
# use name to determine configs
|
||||||
|
config_list = vector.split(".")[0].split("_")
|
||||||
|
operation = "2" #sqrt
|
||||||
|
rounding_mode = round_dict[str(config_list[2])]
|
||||||
|
# use name to create our new tv
|
||||||
|
dest_file = open(dest_dir + "cvw_" + vector, 'a')
|
||||||
|
# open vector
|
||||||
|
src_file = open(source_dir + vector,'r')
|
||||||
|
# for each test in the vector
|
||||||
|
for i in src_file.readlines():
|
||||||
|
translation = "" # this stores the test that we are currently working on
|
||||||
|
[input_1, answer, flags] = i.split("_") # separate inputs, answer, and flags
|
||||||
|
# put it all together, strip nec for removing \n on the end of the flags
|
||||||
|
translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(input_1), "X"*32, ext_bits(answer), flags.strip(), rounding_mode)
|
||||||
|
dest_file.write(translation + "\n")
|
||||||
|
dest_file.close()
|
||||||
|
src_file.close()
|
@ -3,3 +3,6 @@
|
|||||||
mkdir -p vectors
|
mkdir -p vectors
|
||||||
./create_vectors.sh
|
./create_vectors.sh
|
||||||
./remove_spaces.sh
|
./remove_spaces.sh
|
||||||
|
|
||||||
|
# to create tvs for evaluation of combined IFdivsqrt
|
||||||
|
#./combined_IF_vectors/create_IF_vectors.sh
|
@ -53,7 +53,7 @@
|
|||||||
8000000b # mcause value from m ext interrupt
|
8000000b # mcause value from m ext interrupt
|
||||||
00000000 # mtval for mext interrupt (0x0)
|
00000000 # mtval for mext interrupt (0x0)
|
||||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled
|
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled
|
||||||
00000001 # mcause from an instruction access fault
|
00000001 # mcause from an instruction access fault
|
||||||
00000000 # mtval of faulting instruction address (0x0)
|
00000000 # mtval of faulting instruction address (0x0)
|
||||||
|
@ -48,7 +48,7 @@
|
|||||||
00000009 # scause from S mode ecall
|
00000009 # scause from S mode ecall
|
||||||
00000000 # stval of ecall (*** defined to be zero for now)
|
00000000 # stval of ecall (*** defined to be zero for now)
|
||||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||||
0000000b # scause from M mode ecall
|
0000000b # scause from M mode ecall
|
||||||
00000000 # stval of ecall (*** defined to be zero for now)
|
00000000 # stval of ecall (*** defined to be zero for now)
|
||||||
|
@ -45,7 +45,7 @@
|
|||||||
00000008 # scause from U mode ecall
|
00000008 # scause from U mode ecall
|
||||||
00000000 # stval of ecall (*** defined to be zero for now)
|
00000000 # stval of ecall (*** defined to be zero for now)
|
||||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||||
0000000b # scause from M mode ecall
|
0000000b # scause from M mode ecall
|
||||||
00000000 # stval of ecall (*** defined to be zero for now)
|
00000000 # stval of ecall (*** defined to be zero for now)
|
||||||
|
@ -108,8 +108,8 @@
|
|||||||
00000000
|
00000000
|
||||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||||
00000000
|
00000000
|
||||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||||
ffffffff
|
00000000
|
||||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||||
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
|
00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled
|
||||||
00000001 # mcause from an instruction access fault
|
00000001 # mcause from an instruction access fault
|
||||||
|
@ -98,8 +98,8 @@
|
|||||||
00000000
|
00000000
|
||||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||||
00000000
|
00000000
|
||||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||||
ffffffff
|
00000000
|
||||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||||
00000000
|
00000000
|
||||||
0000000b # scause from M mode ecall
|
0000000b # scause from M mode ecall
|
||||||
|
@ -92,8 +92,8 @@
|
|||||||
00000000
|
00000000
|
||||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||||
00000000
|
00000000
|
||||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||||
ffffffff
|
00000000
|
||||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||||
00000000
|
00000000
|
||||||
0000000b # scause from M mode ecall
|
0000000b # scause from M mode ecall
|
||||||
|
Loading…
Reference in New Issue
Block a user