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	Simplification to EBU.
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				@ -40,7 +40,7 @@ module controllerinputstage
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  (input logic HCLK,
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   input logic                 HRESETn,
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   input logic                 Save, Restore, Disable,
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   output logic                Request, Active,
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   output logic                Request,
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   // controller input
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   input logic                 HWRITEin,
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   input logic [2:0]           HSIZEin,
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@ -73,7 +73,6 @@ module controllerinputstage
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  assign Request = HTRANSOut != 2'b00;
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  assign HREADYOut = HREADYin & ~Disable;
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  assign Active = Request & HREADYOut;
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endmodule
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@ -109,7 +109,7 @@ module ebu
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  // input stage IFU
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  controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
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    .Request(IFUReq), .Active(IFUActive),
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    .Request(IFUReq),
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    .HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
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    .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
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    .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
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@ -117,7 +117,7 @@ module ebu
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  // input stage LSU
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  // LSU always has priority so there should never be a need to save and restore the address phase inputs.
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  controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
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    .Request(LSUReq), .Active(LSUActive),
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    .Request(LSUReq),
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    .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
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    .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
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    .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
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@ -138,7 +138,7 @@ module ebu
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  // FSM decides if arbitration needed.  Arbitration is held until the last beat of
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  // a burst is completed.
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  assign both = LSUActive & IFUActive;
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  assign both = LSUReq & IFUReq;
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  flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
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  always_comb 
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    case (CurrState) 
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