diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do
index d45bba64d..e412c2398 100644
--- a/wally-pipelined/regression/wally-buildroot.do
+++ b/wally-pipelined/regression/wally-buildroot.do
@@ -34,19 +34,10 @@ vopt +acc work.testbench -o workopt
 
 vsim workopt -suppress 8852,12070
 
-run 150 ms
-add log -r /*
-do linux-wave.do
-
-run 150 ms
-#run 180 us
-
 #-- Run the Simulation 
-#run -all
-#do ./wave-dos/linux-waves.do
-#run 60 ms
-
-#run -all
+run -all
+do ./wave-dos/linux-waves.do
+run -all
 
 exec ./slack-notifier/slack-notifier.py
 ##quit
diff --git a/wally-pipelined/regression/wave-dos/linux-waves.do b/wally-pipelined/regression/wave-dos/linux-waves.do
index f73aaba7a..ce8b7a5b0 100644
--- a/wally-pipelined/regression/wave-dos/linux-waves.do
+++ b/wally-pipelined/regression/wave-dos/linux-waves.do
@@ -3,7 +3,8 @@ quietly WaveActivateNextPane {} 0
 add wave -noupdate -divider <NULL>
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
-add wave -noupdate -radix decimal /testbench/instrs
+add wave -noupdate -radix decimal /testbench/errorCount
+add wave -noupdate -radix decimal /testbench/InstrCountW
 add wave -noupdate -divider Stalls_and_Flushes
 add wave -noupdate /testbench/dut/hart/StallF
 add wave -noupdate /testbench/dut/hart/StallD
@@ -14,33 +15,15 @@ add wave -noupdate /testbench/dut/hart/FlushD
 add wave -noupdate /testbench/dut/hart/FlushE
 add wave -noupdate /testbench/dut/hart/FlushM
 add wave -noupdate /testbench/dut/hart/FlushW
-add wave -noupdate -divider InstrTranslator
-add wave -noupdate -group InstrTranslator /testbench/SvMode
-add wave -noupdate -group InstrTranslator /testbench/PTE_R
-add wave -noupdate -group InstrTranslator /testbench/PTE_X
-add wave -noupdate -group InstrTranslator /testbench/SATP
-add wave -noupdate -group InstrTranslator /testbench/PTE
-add wave -noupdate -group InstrTranslator /testbench/BaseAdr
-add wave -noupdate -group InstrTranslator /testbench/PAdr
-add wave -noupdate -group InstrTranslator /testbench/VPN
-add wave -noupdate -group InstrTranslator /testbench/Offset
-add wave -noupdate -group InstrTranslator /testbench/readAdrExpected
-add wave -noupdate -group InstrTranslator /testbench/readAdrTranslated
-add wave -noupdate -group InstrTranslator /testbench/writeAdrExpected
-add wave -noupdate -group InstrTranslator /testbench/writeAdrTranslated
 add wave -noupdate -divider F
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCF
 add wave -noupdate -divider D
-add wave -noupdate -radix hexadecimal /testbench/PCDexpected
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD
-add wave -noupdate -radix hexadecimal /testbench/PCtextD
 add wave -noupdate /testbench/InstrDName
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidD
-add wave -noupdate -radix hexadecimal /testbench/PCDwrong
 add wave -noupdate -divider E
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCE
-add wave -noupdate -radix hexadecimal /testbench/PCtextE
 add wave -noupdate /testbench/InstrEName
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidE
@@ -49,7 +32,6 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate -divider M
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM
-add wave -noupdate -radix hexadecimal /testbench/PCtextM
 add wave -noupdate /testbench/InstrMName
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
@@ -80,168 +62,8 @@ add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/Translatio
 add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
 add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/NextWalkerState
 add wave -noupdate -group Walker /testbench/dut/hart/lsu/hptw/genblk1/InitialWalkerState
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/clk
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/reset
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/StallM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/FlushM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/StallW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/FlushW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/LSUStall
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemRWM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/Funct3M
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/Funct7M
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/AtomicM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/ExceptionM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/PendingInterruptM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/CommittedM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/SquashSCW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DataMisalignedM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAdrM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAdrE
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/WriteDataM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/ReadDataW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/PrivilegeModeW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBFlushM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBLoadPageFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBStorePageFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/LoadMisalignedFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/LoadAccessFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/StoreMisalignedFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/StoreAccessFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/CommitM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBPAdrM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBReadM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBWriteM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCfromAHBAck
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCfromAHBReadData
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBWriteData
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCtoAHBSizeM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/SATP_REGW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_MXR
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_SUM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_MPRV
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/STATUS_MPP
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/PCF
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/ITLBMissF
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/PageType
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/ITLBWriteF
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerInstrPageFaultF
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerLoadPageFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerStorePageFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBHitM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/SquashSCM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBPageFaultM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAccessM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/CurrState
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/NextState
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemPAdrM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBMissM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DTLBWriteM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWReadPTE
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWStall
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWPAdrE
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWRead
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemRWMtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/Funct3MtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/AtomicMtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/MemAdrEtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/ReadDataWfromDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/StallWtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DataMisalignedMfromDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/HPTWReady
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DisableTranslation
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/DCacheStall
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/CacheableM
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/CacheableMtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/SelPTW
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/CommittedMfromDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/PendingInterruptMtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/FlushWtoDCache
-add wave -noupdate -group LSU /testbench/dut/hart/lsu/WalkerPageFaultM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/clk
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/reset
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/StallM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/StallW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FlushM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FlushW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct3M
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct7M
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AtomicM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemAdrE
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemPAdrM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DCacheStall
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CommittedM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ExceptionM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/PendingInterruptM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DTLBMissM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DTLBWriteM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ITLBWriteF
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelPTW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBPAdr
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBRead
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBWrite
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AHBAck
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/HRDATA
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/HWDATA
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelAdrM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMAdr
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWriteData
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SetValidM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ClearValidM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SetDirtyM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ClearDirtyM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Valid
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Dirty
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CacheHit
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/NewReplacement
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataWordM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FinalWriteDataM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FinalAMOWriteDataM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FinalWriteDataWordsM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/NextFetchCount
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelMemWriteDataM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct3W
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWriteEnable
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SaveSRAMRead
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AtomicW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimWay
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimDirty
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelAMOWrite
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelUncached
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/Funct7W
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/MemPAdrDecodedW
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/BasePAdrM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/BasePAdrOffsetM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/BasePAdrMaskedM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/AnyCPUReqM
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/FetchCountFlag
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/PreCntEn
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CntEn
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CntReset
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CPUBusy
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/PreviousCPUBusy
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/SelEvict
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/CurrState
-add wave -noupdate -group DCache /testbench/dut/hart/lsu/dcache/NextState
+add wave -noupdate -group LSU -r /testbench/dut/hart/lsu/*
+add wave -noupdate -group DCache -r /testbench/dut/hart/lsu/dcache/*
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/clk
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/reset
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/StallW
@@ -275,7 +97,6 @@ add wave -noupdate -group EBU /testbench/dut/hart/ebu/HMASTLOCK
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/HWRITED
-add wave -noupdate -group EBU /testbench/dut/hart/ebu/CommitM
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/GrantData
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/AccessAddress
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/ISize
@@ -292,15 +113,12 @@ add wave -noupdate -group EBU /testbench/dut/hart/ebu/BusState
 add wave -noupdate -group EBU /testbench/dut/hart/ebu/NextBusState
 add wave -noupdate -divider W
 add wave -noupdate -radix hexadecimal /testbench/PCW
-add wave -noupdate -radix hexadecimal /testbench/PCtextW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
 add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate -divider RegFile
 add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
-add wave -noupdate -radix unsigned /testbench/regNumExpected
 add wave -noupdate -radix unsigned /testbench/dut/hart/ieu/dp/RdW
-add wave -noupdate -radix hexadecimal /testbench/regExpected
 add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3
 add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
 add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}