Formatting

pipelined/src/ebu/ahbinterface.sv

@@ -1,14 +1,13 @@
 ///////////////////////////////////////////
 // ahbinterface.sv
 //
-// Written: Ross Thompson ross1728@gmail.com August 29, 2022
+// Written: Ross Thompson ross1728@gmail.com
-// Modified: 
+// Created: August 29, 2022
+// Modified: 18 January 2023
 //
-// Purpose: Cache/Bus data path.
+// Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ).
-// Bus Side logic
+// 
-// register the fetch data from the next level of memory.
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
-// This register should be necessary for timing.  There is no register in the uncore or
-// ahblite controller between the memories and this cache.
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -30,7 +29,9 @@
 
 `include "wally-config.vh"
 
-module ahbinterface #(parameter LSU = 0) ( // **** modify to use LSU/ifu parameter to control widths of buses
+module ahbinterface #(
+  parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
+)( 
   input logic 							HCLK, HRESETn,
   // bus interface
   input logic 							HREADY,       // AHB peripheral ready

pipelined/src/ebu/busfsm.sv

@@ -1,10 +1,13 @@
 ///////////////////////////////////////////
 // busfsm.sv
 //
-// Written: Ross Thompson ross1728@gmail.com December 29, 2021
+// Written: Ross Thompson ross1728@gmail.com
-// Modified: 
+// Created: December 29, 2021
+// Modified: 18 January 2023
 //
-// Purpose: Load/Store Unit's interface to BUS for cacheless system
+// Purpose: Simple NON_SEQ (no burst) AHB controller.
+//
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 //