Moved WriteDataM register into LSU.

pipelined/src/ieu/datapath.sv

@@ -55,7 +55,7 @@ module datapath (
   input  logic             FWriteIntM,
   input  logic [`XLEN-1:0] FIntResM,
   output logic [`XLEN-1:0] SrcAM,
-  output logic [`XLEN-1:0] WriteDataM, 
+  output logic [`XLEN-1:0] WriteDataE, 
   // Writeback stage signals
   input  logic             StallW, FlushW,
 (* mark_debug = "true" *)  input  logic             RegWriteW, 
@@ -83,7 +83,6 @@ module datapath (
   logic [`XLEN-1:0] SrcAE2, SrcBE2;
 
   logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
-  logic [`XLEN-1:0] WriteDataE;
   // Memory stage signals
   logic [`XLEN-1:0] IEUResultM;
   logic [`XLEN-1:0] IFResultM;
@@ -119,7 +118,6 @@ module datapath (
   // Memory stage pipeline register
   flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
   flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
-  flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
   flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);	
   
   // Writeback stage pipeline register and logic

pipelined/src/ieu/ieu.sv

@@ -52,7 +52,7 @@ module ieu (
   output logic [1:0] 	   MemRWM, // read/write control goes to LSU
   output logic [1:0] 	   AtomicE, // atomic control goes to LSU	    
   output logic [1:0] 	   AtomicM, // atomic control goes to LSU
-  output logic [`XLEN-1:0] WriteDataM, // Address and write data to LSU
+  output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU
 
   output logic [2:0] 	   Funct3M, // size and signedness to LSU
   output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
@@ -106,7 +106,7 @@ module ieu (
     .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
     .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
     .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, 
-    .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM,
+    .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE,
     .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW,
     .CSRReadValW, .ReadDataM, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
   

pipelined/src/lsu/lsu.sv

@@ -50,7 +50,7 @@ module lsu (
    // address and write data
    input logic [`XLEN-1:0]  IEUAdrE,
    (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
-   input logic [`XLEN-1:0]  WriteDataM, 
+   input logic [`XLEN-1:0]  WriteDataE, 
    output logic [`XLEN-1:0] ReadDataM,
    // cpu privilege
    input logic [1:0]        PrivilegeModeW,
@@ -105,10 +105,12 @@ module lsu (
   logic                     DataDAPageFaultM;
   logic [`XLEN-1:0]         LSUWriteDataM;
   logic [(`XLEN-1)/8:0]     ByteMaskM;
+  logic [`XLEN-1:0]         WriteDataM;
   
   // *** TO DO: Burst mode
 
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
+  flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
   assign IEUAdrExtM = {2'b00, IEUAdrM}; 
   assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
 

pipelined/src/wally/wallypipelinedcore.sv

@@ -127,7 +127,7 @@ module wallypipelinedcore (
   // cpu lsu interface
   logic [2:0] 		    Funct3M;
   logic [`XLEN-1:0] 	    IEUAdrE;
-  (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
+  (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataE;
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    IEUAdrM;  
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    ReadDataM;
   logic [`XLEN-1:0] 	    ReadDataW;  
@@ -223,7 +223,7 @@ module wallypipelinedcore (
      .MemRWM, // read/write control goes to LSU
      .AtomicE, // atomic control goes to LSU	    
      .AtomicM, // atomic control goes to LSU
-     .WriteDataM, // Write data to LSU
+     .WriteDataE, // Write data to LSU
      .Funct3M, // size and signedness to LSU
      .SrcAM, // to privilege and fpu
      .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
@@ -252,7 +252,7 @@ module wallypipelinedcore (
 	.CommittedM, .DCacheMiss, .DCacheAccess,
 	.SquashSCW,            
 	//.DataMisalignedM(DataMisalignedM),
-	.IEUAdrE, .IEUAdrM, .WriteDataM,
+	.IEUAdrE, .IEUAdrM, .WriteDataE,
 	.ReadDataM, .FlushDCacheM,
 	// connected to ahb (all stay the same)
 	.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,

pipelined/testbench/testbench-linux.sv

@@ -101,7 +101,7 @@ module testbench;
   flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
   flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
   flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
-  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.WriteDataM, WriteDataW);  
+  flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);  
   flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
 
   ///////////////////////////////////////////////////////////////////////////////