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https://github.com/openhwgroup/cvw
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Moved WriteDataM register into LSU.
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07b7dbc922
commit
58668812c1
@ -55,7 +55,7 @@ module datapath (
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input logic FWriteIntM,
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input logic FWriteIntM,
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input logic [`XLEN-1:0] FIntResM,
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input logic [`XLEN-1:0] FIntResM,
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output logic [`XLEN-1:0] SrcAM,
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output logic [`XLEN-1:0] SrcAM,
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output logic [`XLEN-1:0] WriteDataM,
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output logic [`XLEN-1:0] WriteDataE,
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// Writeback stage signals
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// Writeback stage signals
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input logic StallW, FlushW,
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input logic StallW, FlushW,
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(* mark_debug = "true" *) input logic RegWriteW,
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(* mark_debug = "true" *) input logic RegWriteW,
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@ -83,7 +83,6 @@ module datapath (
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logic [`XLEN-1:0] SrcAE2, SrcBE2;
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logic [`XLEN-1:0] SrcAE2, SrcBE2;
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logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
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logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
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logic [`XLEN-1:0] WriteDataE;
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// Memory stage signals
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// Memory stage signals
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logic [`XLEN-1:0] IEUResultM;
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logic [`XLEN-1:0] IEUResultM;
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logic [`XLEN-1:0] IFResultM;
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logic [`XLEN-1:0] IFResultM;
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@ -119,7 +118,6 @@ module datapath (
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// Memory stage pipeline register
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// Memory stage pipeline register
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flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
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flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
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flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
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flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
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flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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// Writeback stage pipeline register and logic
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// Writeback stage pipeline register and logic
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@ -52,7 +52,7 @@ module ieu (
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] AtomicE, // atomic control goes to LSU
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output logic [1:0] AtomicE, // atomic control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [`XLEN-1:0] WriteDataM, // Address and write data to LSU
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output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU
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output logic [2:0] Funct3M, // size and signedness to LSU
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output logic [2:0] Funct3M, // size and signedness to LSU
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output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
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output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
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@ -106,7 +106,7 @@ module ieu (
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.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
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.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
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.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
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.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
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.FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
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.FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
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.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM,
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.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE,
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.StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW,
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.StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW,
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.CSRReadValW, .ReadDataM, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
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.CSRReadValW, .ReadDataM, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
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@ -50,7 +50,7 @@ module lsu (
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// address and write data
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// address and write data
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input logic [`XLEN-1:0] IEUAdrE,
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input logic [`XLEN-1:0] IEUAdrE,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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(* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [`XLEN-1:0] WriteDataE,
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output logic [`XLEN-1:0] ReadDataM,
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output logic [`XLEN-1:0] ReadDataM,
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// cpu privilege
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// cpu privilege
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input logic [1:0] PrivilegeModeW,
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input logic [1:0] PrivilegeModeW,
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@ -105,10 +105,12 @@ module lsu (
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logic DataDAPageFaultM;
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logic DataDAPageFaultM;
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logic [`XLEN-1:0] LSUWriteDataM;
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logic [`XLEN-1:0] LSUWriteDataM;
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logic [(`XLEN-1)/8:0] ByteMaskM;
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logic [(`XLEN-1)/8:0] ByteMaskM;
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logic [`XLEN-1:0] WriteDataM;
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// *** TO DO: Burst mode
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// *** TO DO: Burst mode
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
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flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign IEUAdrExtM = {2'b00, IEUAdrM};
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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assign LSUStallM = DCacheStallM | InterlockStall | BusStall;
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@ -127,7 +127,7 @@ module wallypipelinedcore (
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// cpu lsu interface
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// cpu lsu interface
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logic [2:0] Funct3M;
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] IEUAdrE;
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logic [`XLEN-1:0] IEUAdrE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
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logic [`XLEN-1:0] ReadDataW;
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logic [`XLEN-1:0] ReadDataW;
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@ -223,7 +223,7 @@ module wallypipelinedcore (
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.MemRWM, // read/write control goes to LSU
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.MemRWM, // read/write control goes to LSU
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.AtomicE, // atomic control goes to LSU
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.AtomicE, // atomic control goes to LSU
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.AtomicM, // atomic control goes to LSU
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.AtomicM, // atomic control goes to LSU
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.WriteDataM, // Write data to LSU
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.WriteDataE, // Write data to LSU
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.Funct3M, // size and signedness to LSU
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.Funct3M, // size and signedness to LSU
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.SrcAM, // to privilege and fpu
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.SrcAM, // to privilege and fpu
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.RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
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.RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
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@ -252,7 +252,7 @@ module wallypipelinedcore (
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.CommittedM, .DCacheMiss, .DCacheAccess,
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.SquashSCW,
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.SquashSCW,
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//.DataMisalignedM(DataMisalignedM),
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//.DataMisalignedM(DataMisalignedM),
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.IEUAdrE, .IEUAdrM, .WriteDataM,
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.IEUAdrE, .IEUAdrM, .WriteDataE,
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.ReadDataM, .FlushDCacheM,
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.ReadDataM, .FlushDCacheM,
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// connected to ahb (all stay the same)
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// connected to ahb (all stay the same)
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.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,
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.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,
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@ -101,7 +101,7 @@ module testbench;
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flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
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flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.core.ifu.InstrM, InstrW);
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flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
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flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.core.ieu.c.InstrValidM, InstrValidW);
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flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
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flopenrc #(`XLEN) IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.IEUAdrM, IEUAdrW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.WriteDataM, WriteDataW);
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flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.core.lsu.WriteDataM, WriteDataW);
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flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
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flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.core.hzu.TrapM, TrapW);
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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