diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt
index 1d23c29a2..a50091827 100644
--- a/fpga/constraints/marked_debug.txt
+++ b/fpga/constraints/marked_debug.txt
@@ -5,3 +5,22 @@ wally/wallypipelinedcore.sv: logic                 InstrM
 lsu/lsu.sv: logic        IEUAdrM
 lsu/lsu.sv: logic       MemRWM
 mmu/hptw.sv: logic	   SATP_REGW
+uncore/spi_apb.sv: logic ShiftIn
+uncore/spi_apb.sv: logic  ReceiveShiftReg
+uncore/spi_apb.sv: logic  SCLKenable
+uncore/spi_apb.sv: logic  SampleEdge
+uncore/spi_apb.sv: logic  Active
+uncore/spi_apb.sv: statetype state
+uncore/spi_apb.sv: typedef rsrstatetype
+uncore/spi_apb.sv: logic SPICLK
+uncore/spi_apb.sv: logic SPIOut
+uncore/spi_apb.sv: logic SPICS
+uncore/spi_apb.sv: logic SckMode
+uncore/spi_apb.sv: logic SckDiv
+uncore/spi_apb.sv: logic ShiftEdge
+uncore/spi_apb.sv: logic TransmitShiftRegLoad
+uncore/spi_apb.sv: logic TransmitShiftReg
+uncore/spi_apb.sv: logic TransmitData
+uncore/spi_apb.sv: logic ReceiveData
+uncore/spi_apb.sv: logic ReceiveShiftRegEndian
+uncore/spi_apb.sv: logic ASR
diff --git a/fpga/constraints/small-debug-spi.xdc b/fpga/constraints/small-debug-spi.xdc
index f62e3d4d3..5951bdcb8 100644
--- a/fpga/constraints/small-debug-spi.xdc
+++ b/fpga/constraints/small-debug-spi.xdc
@@ -191,7 +191,6 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe33]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
 connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadEmpty} ]]  
 
-
 # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock.
 #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk]
 connect_debug_port dbg_hub/clk [get_nets CPUCLK]
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 7ffd9f163..52e46ec38 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -69,8 +69,8 @@ PreProcessFiles:
 	./insert_debug_comment.sh
 	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
 	sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
-	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
-	sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
+	sed -i 's/$$WALLY/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
 
 # build the Zero stage boot loader (ZSBL)
 .PHONY: zsbl
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 3ca0c3360..7935b5913 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -102,7 +102,8 @@ if {$board=="ArtyA7"} {
 } else {
     #source ../constraints/vcu-small-debug.xdc
     #source ../constraints/small-debug.xdc
-    source ../constraints/small-debug-spi.xdc
+    #source ../constraints/small-debug.xdc
+    source ../constraints/big-debug-spi.xdc
 }