From 57c366c1b24844eeee2fdfcfe8afe467bd315d7e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 17 Sep 2022 22:01:03 -0500
Subject: [PATCH] Removed NonIROM and NonDTIM select signals from IFU and LSU.

---
 pipelined/src/ifu/ifu.sv | 15 ++++++---------
 pipelined/src/lsu/lsu.sv | 10 ++--------
 2 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index cde1e02b5..ab84ac929 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -92,7 +92,7 @@ module ifu (
   logic                        CompressedF;
   logic [31:0]                 InstrRawD, InstrRawF;
   logic [31:0]                 FinalInstrRawF;
-  logic [1:0]                  NonIROMMemRWM;
+  logic [1:0]                  RWF;
   
   logic [31:0]                 InstrE;
   logic [`XLEN-1:0]            PCD;
@@ -113,7 +113,6 @@ module ifu (
   logic 					   BusStall;
   logic 					   ICacheStallF, IFUCacheBusStallF;
   logic 					   CPUBusy;
-  logic              SelIROM;
 (* mark_debug = "true" *)  logic [31:0] 				   PostSpillInstrRawF;
   // branch predictor signal
   logic [`XLEN-1:0]            PCNext1F, PCNext2F, PCNext0F;
@@ -193,13 +192,11 @@ module ifu (
     assign IROMAdr = CPUBusy | reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
  
-    adrdec iromdec(PCFExt, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, 1'b1, 2'b10, 4'b1111, SelIROM);
-    //assign NonIROMMemRWM = {~SelIROM, 1'b0};
-    assign NonIROMMemRWM = 2'b10;
+    assign RWF = 2'b10;
     irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
  
   end else begin
-    assign SelIROM = 0; assign NonIROMMemRWM = 2'b10;
+    assign RWF = 2'b10;
   end
   if (`BUS) begin : bus
     localparam integer   WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
@@ -213,7 +210,7 @@ module ifu (
       logic [1:0]          CacheRW, RW;
       
       assign CacheRW = {ICacheFetchLine, 1'b0} & ~{ITLBMissF, ITLBMissF};
-      assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
+      assign RW = RWF & ~{ITLBMissF, ITLBMissF} & ~{CacheableF, CacheableF};
       cache #(.LINELEN(`ICACHE_LINELENINBITS),
               .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
               .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
@@ -227,7 +224,7 @@ module ifu (
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
              .ByteMask('0), .WordCount('0), .SelBusWord('0),
              .FinalWriteData('0),
-             .RW(NonIROMMemRWM), 
+             .RW(RWF), 
              .Atomic('0), .FlushCache('0),
              .NextAdr(PCNextFSpill[11:0]),
              .PAdr(PCPF),
@@ -249,7 +246,7 @@ module ifu (
       assign IFUHADDR = PCPF;
       logic CaptureEn;
       logic [1:0] RW;
-      assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF};
+      assign RW = RWF & ~{ITLBMissF, ITLBMissF};
       assign IFUHSIZE = 3'b010;
 
       ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), 
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 599c6803a..a269d1a8f 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -130,7 +130,7 @@ module lsu (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
-    lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM(NonDTIMMemRWM), .AtomicM, .ITLBMissF, .ITLBWriteF,
+    lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .SelReplay,
       .TrapM, .DCacheStallM, .SATP_REGW, .PCF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
@@ -140,7 +140,7 @@ module lsu (
       .IgnoreRequestTLB);
   end else begin
     assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0;
-    assign CPUBusy = StallW; assign PreLSURWM = NonDTIMMemRWM; 
+    assign CPUBusy = StallW; assign PreLSURWM = MemRWM; 
     assign IHAdrM = IEUAdrExtM;
     assign LSUFunct3M = Funct3M;  assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM;
     assign IMWriteDataM = WriteDataM;
@@ -207,7 +207,6 @@ module lsu (
   
   if (`DTIM_SUPPORTED) begin : dtim
     logic [`PA_BITS-1:0] DTIMAdr;
-    logic             DTIMAccessRW;
     logic             MemStage;
 
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
@@ -216,11 +215,6 @@ module lsu (
     assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
     assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
-    assign DTIMAccessRW = |MemRWM;
-    // *** Ross remove this.
-    adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu?
-    //assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected
-    assign NonDTIMMemRWM = MemRWM; // *** fix
 
     dtim dtim(.clk, .reset, .MemRWM,
               .Adr(DTIMAdr),