diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index e0e6ab288..1d23c29a2 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -5,18 +5,3 @@ wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM lsu/lsu.sv: logic MemRWM mmu/hptw.sv: logic SATP_REGW -uncore/spi_apb.sv: logic ShiftIn -uncore/spi_apb.sv: logic ReceiveShiftReg -uncore/spi_apb.sv: logic SCLKenable -uncore/spi_apb.sv: logic SampleEdge -uncore/spi_apb.sv: logic Active -uncore/spi_apb.sv: statetype state -uncore/spi_apb.sv: typedef rsrstatetype -uncore/spi_apb.sv: logic SPICLK -uncore/spi_apb.sv: logic SPIOut -uncore/spi_apb.sv: logic SPICS -uncore/spi_apb.sv: logic SckMode -uncore/spi_apb.sv: logic SckDiv -uncore/spi_apb.sv: logic ShiftEdge -uncore/spi_apb.sv: logic TransmitShiftRegLoad -uncore/spi_apb.sv: logic TransmitShiftReg diff --git a/fpga/constraints/marked_debug_spi.txt b/fpga/constraints/marked_debug_spi.txt new file mode 100644 index 000000000..c840f6b99 --- /dev/null +++ b/fpga/constraints/marked_debug_spi.txt @@ -0,0 +1,36 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic MemRWM +mmu/hptw.sv: logic SATP_REGW +uncore/spi_apb.sv: logic ShiftIn +uncore/spi_apb.sv: logic ReceiveShiftReg +uncore/spi_apb.sv: logic SCLKenable +uncore/spi_apb.sv: logic SampleEdge +uncore/spi_apb.sv: logic Active +uncore/spi_apb.sv: statetype state +uncore/spi_apb.sv: typedef rsrstatetype +uncore/spi_apb.sv: logic SPICLK +uncore/spi_apb.sv: logic SPIOut +uncore/spi_apb.sv: logic SPICS +uncore/spi_apb.sv: logic SckMode +uncore/spi_apb.sv: logic SckDiv +uncore/spi_apb.sv: logic ShiftEdge +uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle +uncore/spi_apb.sv: logic TransmitShiftReg +uncore/spi_apb.sv: logic TransmitData +uncore/spi_apb.sv: logic ReceiveData +uncore/spi_apb.sv: logic ReceiveShiftRegEndian +uncore/spi_apb.sv: logic TransmitShiftReg +uncore/spi_apb.sv: logic TransmitShift +uncore/spi_apb.sv: logic ReceiveShiftFullDelay +uncore/spi_apb.sv: logic TransmitShiftEmpty +uncore/spi_apb.sv: logic ReceiveFIFOWriteFull +uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement +uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty +uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement +uncore/spi_apb.sv: logic TransmitFIFOReadIncrement +uncore/spi_apb.sv: logic TransmitFIFOWriteFull +uncore/spi_apb.sv: logic TransmitFIFOReadEmpty diff --git a/fpga/constraints/small-debug-spi.xdc b/fpga/constraints/small-debug-spi.xdc index 5e199587b..f62e3d4d3 100644 --- a/fpga/constraints/small-debug-spi.xdc +++ b/fpga/constraints/small-debug-spi.xdc @@ -3,7 +3,7 @@ create_debug_core u_ila_0 ila -set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 65536 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] @@ -122,9 +122,75 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ShiftEdge} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe20] +set_property port_width 8 [get_debug_ports u_ila_0/probe20] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftRegLoad} ]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftReg[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveData[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftRegEndian[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 9 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[3]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[4]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[5]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[6]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[7]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitData[8]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveShiftFullDelay} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftRegLoadSingleCycle} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitShiftEmpty} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOWriteFull} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadIncrement} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadEmpty} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteIncrement} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadIncrement} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe32] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOWriteFull} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe33] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitFIFOReadEmpty} ]] + # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 5207680df..5151b0e77 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -98,6 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc + #source ../constraints/small-debug-spi.xdc } else { #source ../constraints/vcu-small-debug.xdc #source ../constraints/small-debug.xdc diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 5b0580695..0e94f4883 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x17D7840>; - timebase-frequency = <0x17D7840>; + clock-frequency = <20000000>; + timebase-frequency = <20000000>; cpu@0 { phandle = <0x01>; @@ -54,7 +54,7 @@ refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0x17D7840>; + clock-frequency = <20000000>; clock-output-names = "xtal"; }; @@ -73,7 +73,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x17D7840>; + clock-frequency = <20000000>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -102,7 +102,7 @@ mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; - spi-max-frequency = <5000000>; + spi-max-frequency = <1000000>; voltage-ranges = <3300 3300>; disable-wp; // gpios = <&gpio0 6 1>; diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 6af9a1388..91021e2b6 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -99,6 +99,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( /* verilator lint_off UNDRIVEN */ logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission) rsrstatetype ReceiveState; + logic ReceiveFiFoTakingData; // Transmission signals logic ZeroDiv; // High when SckDiv is 0 @@ -153,8 +154,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( - - // APB access assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase