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https://github.com/openhwgroup/cvw
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Might actually have a correct implementation of local history branch prediction.
This commit is contained in:
Ross Thompson
parent
e81445be5d
commit
5777b90407
@ -128,14 +128,10 @@ module bpred (
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.BranchE, .BranchM, .PCSrcE);
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end else if (`BPRED_TYPE == "BP_LOCAL") begin:Predictor
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localHistoryPredictor DirPredictor(.clk,
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.reset, .StallD, .StallF, .StallE, .FlushD, .FlushE,
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.LookUpPC(PCNextF),
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.BPDirPredF,
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// update
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.UpdatePC(PCE),
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.UpdateEN(BranchE & ~StallE),
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.PCSrcE);
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localHistoryPredictor #(6, 10)
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DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
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.BranchE, .BranchM, .PCSrcE);
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end
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// Part 2 Branch target address prediction
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@ -1,10 +1,11 @@
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///////////////////////////////////////////
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// locallHistoryPredictor.sv
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// gsharebasic.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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// Written: Ross Thompson
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// Email: ross1728@gmail.com
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// Created: 16 March 2021
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// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
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// Modified: 20 February 2023
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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@ -28,114 +29,73 @@
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`include "wally-config.vh"
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module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
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k = 10) ( // number of past branches stored
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input logic clk,
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input logic reset,
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input logic StallD, StallF, StallE,
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input logic FlushD, FlushE,
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input logic [`XLEN-1:0] LookUpPC,
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output logic [1:0] BPDirPredF,
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module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
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parameter k = 10) ( // number of past branches stored
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic [1:0] BPDirPredF,
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output logic BPDirPredWrongE,
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// update
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input logic [`XLEN-1:0] UpdatePC,
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input logic UpdateEN, PCSrcE
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input logic [`XLEN-1:0] PCNextF, PCM,
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input logic BranchE, BranchM, PCSrcE
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);
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logic [2**m-1:0][k-1:0] LHRNextF;
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logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
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logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
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logic [1:0] PredictionMemory;
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logic DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
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logic [1:0] UpdatePredictionF;
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logic [1:0] BPDirPredD, BPDirPredE;
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logic [1:0] NewBPDirPredE, NewBPDirPredM;
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logic [k-1:0] IndexNextF, IndexM;
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logic [1:0] BPDirPredD, BPDirPredE;
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logic [1:0] NewBPDirPredE, NewBPDirPredM;
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logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
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logic [k-1:0] GHRNext;
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logic PCSrcM;
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logic [2**m-1:0][k-1:0] LHR;
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logic [m-1:0] IndexLHRNextF, IndexLHRM;
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logic UpdateM;
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assign LHRFNext = {PCSrcE, LHRF[k-1:1]};
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assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
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assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};
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// INCASE we do ahead pipelining
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// ram2p1r1wb #(m,k) LHR(.clk(clk)),
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// .reset(reset),
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// .RA1(LookUpPCIndex), // need hashing function to get correct PC address
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// .RD1(LHRF),
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// .REN1(~StallF),
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// .WA1(UpdatePCIndex),
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// .WD1(LHRENExt),
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// .WEN1(UpdateEN),
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// .BitWEN1(2'b11));
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genvar index;
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for (index = 0; index < 2**m; index = index +1) begin:localhist
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flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
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.d(LHRFNext), .q(LHRNextF[index]));
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end
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// need to forward when updating to the same address as reading.
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// first we compare to see if the update and lookup addreses are the same
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assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
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assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex];
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// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
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// LHR referes to the address that the past k branches points to in the prediction stage
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// LHRE refers to the address that the past k branches points to in the exectution stage
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assign IndexNextF = GHRNext;
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assign IndexM = GHRM;
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(UpdateEN),
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.ra1(ForwardLHRNext),
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.rd1(PredictionMemory),
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.wa2(LHRFNext),
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.wd2(NewBPDirPredE),
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.we2(UpdateEN),
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.ce1(~StallF), .ce2(~StallW & ~FlushW),
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.ra1(IndexNextF),
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.rd1(BPDirPredF),
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.wa2(IndexM),
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.wd2(NewBPDirPredM),
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.we2(BranchM),
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.bwe2(1'b1));
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assign DoForwardingPHT = LHRFNext == ForwardLHRNext;
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// register the update value and the forwarding signal into the Fetch stage
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// TODO: add stall logic ***
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flopr #(1) DoForwardingReg(.clk(clk),
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.reset(reset),
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.d(DoForwardingPHT),
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.q(DoForwardingPHTF));
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flopr #(2) UpdatePredictionReg(.clk(clk),
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.reset(reset),
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.d(NewBPDirPredE),
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.q(UpdatePredictionF));
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assign BPDirPredF = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD);
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flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE);
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//pipeline for LHR
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flopenrc #(k) LHRFReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.clear(1'b0),
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.d(ForwardLHRNext),
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.q(LHRF));
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
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/*
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flopenrc #(k) LHRDReg(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(FlushD),
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.d(LHRF),
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.q(LHRD));
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flopenrc #(k) LHREReg(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.clear(FlushE),
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.d(LHRD),
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.q(LHRE));
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*/
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flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
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assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
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assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
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// this is local history
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genvar index;
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assign UpdateM = BranchM & ~StallM & ~FlushM;
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assign IndexLHRM = {PCM[m+1] ^ PCM[1], PCM[m:2]};
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for (index = 0; index < 2**m; index = index +1) begin:localhist
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flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateM & (index == IndexLHRM)),
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.d(GHRNext), .q(LHR[index]));
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end
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assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
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assign GHR = LHR[IndexLHRNextF];
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// this is global history
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//flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
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flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
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flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
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flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
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endmodule
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