cache cleanup

pipelined/src/cache/cacheLRU.sv

@@ -27,22 +27,27 @@
 `include "wally-config.vh"
 
 module cacheLRU
-  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)(
-   input logic                clk, reset, CacheEn, FlushStage,
+  #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
+  input  logic                clk, reset, 
+  input  logic                CacheEn, 
+  input  logic                FlushStage,
   input  logic [NUMWAYS-1:0]  HitWay,
   input  logic [NUMWAYS-1:0]  ValidWay,
-   output logic [NUMWAYS-1:0] VictimWay,
   input  logic [SETLEN-1:0]   CAdr,
   input  logic [SETLEN-1:0]   PAdr,
-   input logic                LRUWriteEn, SetValid, InvalidateCache, FlushCache);
+  input  logic                LRUWriteEn, 
+  input  logic                SetValid, 
+  input  logic                InvalidateCache, 
+  input  logic                FlushCache,
+  output logic [NUMWAYS-1:0]  VictimWay
+);
+
+  localparam                           LOGNUMWAYS = $clog2(NUMWAYS);
 
   logic [NUMWAYS-2:0]                  LRUMemory [NUMLINES-1:0];
   logic [NUMWAYS-2:0]                  CurrLRU;
   logic [NUMWAYS-2:0]                  NextLRU;
   logic [NUMWAYS-1:0]                  Way;
-
-  localparam                           LOGNUMWAYS = $clog2(NUMWAYS);
-
   logic [LOGNUMWAYS-1:0]               WayEncoded;
   logic [NUMWAYS-2:0]                  WayExpanded;
   logic                                AllValid;

pipelined/src/cache/cachefsm.sv

@@ -26,8 +26,8 @@
 
 `include "wally-config.vh"
 
-module cachefsm
-  (input logic clk,
+module cachefsm (
+  input  logic       clk,
   input  logic       reset,
   // inputs from IEU
   input  logic       FlushStage,
@@ -67,7 +67,8 @@ module cachefsm
   output logic       FlushWayCntEn, 
   output logic       FlushCntRst,
   output logic       SelFetchBuffer, 
-   output logic       CacheEn);
+  output logic       CacheEn
+);
   
   logic               resetDelay;
   logic               AMO, StoreAMO;
@@ -75,7 +76,7 @@ module cachefsm
   logic               AnyMiss;
   logic               FlushFlag;
     
-  typedef enum logic [3:0]		  {STATE_READY, // hit states
+  typedef enum logic [3:0]{STATE_READY, // hit states
                                    // miss states
 					               STATE_FETCH,
 					               STATE_WRITEBACK,

pipelined/src/cache/cacheway.sv

@@ -26,8 +26,8 @@
 
 `include "wally-config.vh"
 
-module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
-				  parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (
+module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
+				          OFFSETLEN = 5, INDEXLEN = 9, DIRTY_BITS = 1) (
   input  logic                        clk,
   input  logic                        CacheEn,
   input  logic                        reset,
@@ -44,7 +44,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   input  logic                        FlushWay,
   input  logic                        InvalidateCache,
   input  logic                        FlushStage,
-//  input logic [(`XLEN-1)/8:0]        ByteMask,
   input  logic [LINELEN/8-1:0]        LineByteMask,
 
   output logic [LINELEN-1:0]          ReadDataLineWay,
@@ -76,7 +75,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic                               SelData;
   logic                               FlushWayEn, VictimWayEn;
 
-
   // FlushWay and VictimWay are part of a one hot way selection.  Must clear them if FlushWay not selected
   // or VictimWay not selected.
   assign FlushWayEn = FlushWay & SelFlush;

pipelined/src/cache/subcachelineread.sv

@@ -29,24 +29,25 @@
 module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0]   PAdr,
   input  logic [LINELEN-1:0]                                         ReadDataLine,
-  output logic [WORDLEN-1:0] ReadDataWord);
+  output logic [WORDLEN-1:0]                                         ReadDataWord
+);
 
   localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
-  // pad is for icache. Muxing extends over the cacheline boundary.
   localparam PADLEN = WORDLEN-MUXINTERVAL;
+
+  // pad is for icache. Muxing extends over the cacheline boundary.
   logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0]   ReadDataLinePad;
   logic [WORDLEN-1:0]                         ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
 
   if (PADLEN > 0) begin
-    logic [PADLEN-1:0]  Pad;
-    assign Pad = '0;
-    assign ReadDataLinePad = {Pad, ReadDataLine};    
+    assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};    
   end else assign ReadDataLinePad = ReadDataLine;
 
   genvar index;
   for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
-	  assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)];
+	  assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
   end
+  
   // variable input mux
   assign ReadDataWord = ReadDataLineSets[PAdr];
 endmodule