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cache cleanup

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This commit is contained in:
David Harris 2023-01-14 19:43:29 -08:00
parent 08fca1c517
commit 56dac4be7d
4 changed files with 134 additions and 129 deletions
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27
pipelined/src/cache/cacheLRU.sv vendored
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@ -27,22 +27,27 @@
`include "wally-config.vh" `include "wally-config.vh"
module cacheLRU module cacheLRU
#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
input logic clk, reset, CacheEn, FlushStage, input logic clk, reset,
input logic [NUMWAYS-1:0] HitWay, input logic CacheEn,
input logic [NUMWAYS-1:0] ValidWay, input logic FlushStage,
output logic [NUMWAYS-1:0] VictimWay, input logic [NUMWAYS-1:0] HitWay,
input logic [SETLEN-1:0] CAdr, input logic [NUMWAYS-1:0] ValidWay,
input logic [SETLEN-1:0] PAdr, input logic [SETLEN-1:0] CAdr,
input logic LRUWriteEn, SetValid, InvalidateCache, FlushCache); input logic [SETLEN-1:0] PAdr,
input logic LRUWriteEn,
input logic SetValid,
input logic InvalidateCache,
input logic FlushCache,
output logic [NUMWAYS-1:0] VictimWay
);
localparam LOGNUMWAYS = $clog2(NUMWAYS);
logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0]; logic [NUMWAYS-2:0] LRUMemory [NUMLINES-1:0];
logic [NUMWAYS-2:0] CurrLRU; logic [NUMWAYS-2:0] CurrLRU;
logic [NUMWAYS-2:0] NextLRU; logic [NUMWAYS-2:0] NextLRU;
logic [NUMWAYS-1:0] Way; logic [NUMWAYS-1:0] Way;
localparam LOGNUMWAYS = $clog2(NUMWAYS);
logic [LOGNUMWAYS-1:0] WayEncoded; logic [LOGNUMWAYS-1:0] WayEncoded;
logic [NUMWAYS-2:0] WayExpanded; logic [NUMWAYS-2:0] WayExpanded;
logic AllValid; logic AllValid;

121
pipelined/src/cache/cachefsm.sv vendored
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@ -26,48 +26,49 @@
`include "wally-config.vh" `include "wally-config.vh"
module cachefsm module cachefsm (
(input logic clk, input logic clk,
input logic reset, input logic reset,
// inputs from IEU // inputs from IEU
input logic FlushStage, input logic FlushStage,
input logic [1:0] CacheRW, input logic [1:0] CacheRW,
input logic [1:0] CacheAtomic, input logic [1:0] CacheAtomic,
input logic FlushCache, input logic FlushCache,
input logic InvalidateCache, input logic InvalidateCache,
// hazard inputs // hazard inputs
input logic Stall, input logic Stall,
// Bus inputs // Bus inputs
input logic CacheBusAck, input logic CacheBusAck,
// dcache internals // dcache internals
input logic CacheHit, input logic CacheHit,
input logic LineDirty, input logic LineDirty,
input logic FlushAdrFlag, input logic FlushAdrFlag,
input logic FlushWayFlag, input logic FlushWayFlag,
// hazard outputs // hazard outputs
output logic CacheStall, output logic CacheStall,
// counter outputs // counter outputs
output logic CacheMiss, output logic CacheMiss,
output logic CacheAccess, output logic CacheAccess,
// Bus outputs // Bus outputs
output logic CacheCommitted, output logic CacheCommitted,
output logic [1:0] CacheBusRW, output logic [1:0] CacheBusRW,
// dcache internals // dcache internals
output logic SelAdr, output logic SelAdr,
output logic ClearValid, output logic ClearValid,
output logic ClearDirty, output logic ClearDirty,
output logic SetDirty, output logic SetDirty,
output logic SetValid, output logic SetValid,
output logic SelWriteback, output logic SelWriteback,
output logic LRUWriteEn, output logic LRUWriteEn,
output logic SelFlush, output logic SelFlush,
output logic FlushAdrCntEn, output logic FlushAdrCntEn,
output logic FlushWayCntEn, output logic FlushWayCntEn,
output logic FlushCntRst, output logic FlushCntRst,
output logic SelFetchBuffer, output logic SelFetchBuffer,
output logic CacheEn); output logic CacheEn
);
logic resetDelay; logic resetDelay;
logic AMO, StoreAMO; logic AMO, StoreAMO;
@ -75,7 +76,7 @@ module cachefsm
logic AnyMiss; logic AnyMiss;
logic FlushFlag; logic FlushFlag;
typedef enum logic [3:0] {STATE_READY, // hit states typedef enum logic [3:0]{STATE_READY, // hit states
// miss states // miss states
STATE_FETCH, STATE_FETCH,
STATE_WRITEBACK, STATE_WRITEBACK,
@ -111,28 +112,28 @@ module cachefsm
always_comb begin always_comb begin
NextState = STATE_READY; NextState = STATE_READY;
case (CurrState) case (CurrState)
STATE_READY: if(InvalidateCache) NextState = STATE_READY; STATE_READY: if(InvalidateCache) NextState = STATE_READY;
else if(FlushCache) NextState = STATE_FLUSH; else if(FlushCache) NextState = STATE_FLUSH;
// Delayed LRU update. Cannot check if victim line is dirty on this cycle. // Delayed LRU update. Cannot check if victim line is dirty on this cycle.
// To optimize do the fetch first, then eviction if necessary. // To optimize do the fetch first, then eviction if necessary.
else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH; else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH;
else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
else NextState = STATE_FETCH; else NextState = STATE_FETCH;
STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
else NextState = STATE_WRITEBACK; else NextState = STATE_WRITEBACK;
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
else if (FlushFlag) NextState = STATE_READ_HOLD; else if (FlushFlag) NextState = STATE_READ_HOLD;
else NextState = STATE_FLUSH; else NextState = STATE_FLUSH;
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
else if(CacheBusAck) NextState = STATE_READ_HOLD; else if(CacheBusAck) NextState = STATE_READ_HOLD;
else NextState = STATE_FLUSH_WRITEBACK; else NextState = STATE_FLUSH_WRITEBACK;
default: NextState = STATE_READY; default: NextState = STATE_READY;
endcase endcase
end end

92
pipelined/src/cache/cacheway.sv vendored
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@ -26,56 +26,54 @@
`include "wally-config.vh" `include "wally-config.vh"
module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) ( OFFSETLEN = 5, INDEXLEN = 9, DIRTY_BITS = 1) (
input logic clk, input logic clk,
input logic CacheEn, input logic CacheEn,
input logic reset, input logic reset,
input logic [$clog2(NUMLINES)-1:0] CAdr, input logic [$clog2(NUMLINES)-1:0] CAdr,
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic [LINELEN-1:0] LineWriteData, input logic [LINELEN-1:0] LineWriteData,
input logic SetValid, input logic SetValid,
input logic ClearValid, input logic ClearValid,
input logic SetDirty, input logic SetDirty,
input logic ClearDirty, input logic ClearDirty,
input logic SelWriteback, input logic SelWriteback,
input logic SelFlush, input logic SelFlush,
input logic VictimWay, input logic VictimWay,
input logic FlushWay, input logic FlushWay,
input logic InvalidateCache, input logic InvalidateCache,
input logic FlushStage, input logic FlushStage,
// input logic [(`XLEN-1)/8:0] ByteMask, input logic [LINELEN/8-1:0] LineByteMask,
input logic [LINELEN/8-1:0] LineByteMask,
output logic [LINELEN-1:0] ReadDataLineWay, output logic [LINELEN-1:0] ReadDataLineWay,
output logic HitWay, output logic HitWay,
output logic ValidWay, output logic ValidWay,
output logic DirtyWay, output logic DirtyWay,
output logic [TAGLEN-1:0] TagWay); output logic [TAGLEN-1:0] TagWay);
localparam integer WORDSPERLINE = LINELEN/`XLEN; localparam integer WORDSPERLINE = LINELEN/`XLEN;
localparam integer BYTESPERLINE = LINELEN/8; localparam integer BYTESPERLINE = LINELEN/8;
localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGWPL = $clog2(WORDSPERLINE);
localparam LOGXLENBYTES = $clog2(`XLEN/8); localparam LOGXLENBYTES = $clog2(`XLEN/8);
localparam integer BYTESPERWORD = `XLEN/8; localparam integer BYTESPERWORD = `XLEN/8;
logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLine;
logic [TAGLEN-1:0] ReadTag;
logic Dirty;
logic SelTag;
logic SelectedWriteWordEn;
logic [LINELEN/8-1:0] FinalByteMask;
logic SetValidEN;
logic SetValidWay;
logic ClearValidWay;
logic SetDirtyWay;
logic ClearDirtyWay;
logic SelNonHit;
logic SelData;
logic FlushWayEn, VictimWayEn;
logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits;
logic [LINELEN-1:0] ReadDataLine;
logic [TAGLEN-1:0] ReadTag;
logic Dirty;
logic SelTag;
logic SelectedWriteWordEn;
logic [LINELEN/8-1:0] FinalByteMask;
logic SetValidEN;
logic SetValidWay;
logic ClearValidWay;
logic SetDirtyWay;
logic ClearDirtyWay;
logic SelNonHit;
logic SelData;
logic FlushWayEn, VictimWayEn;
// FlushWay and VictimWay are part of a one hot way selection. Must clear them if FlushWay not selected // FlushWay and VictimWay are part of a one hot way selection. Must clear them if FlushWay not selected
// or VictimWay not selected. // or VictimWay not selected.

21
pipelined/src/cache/subcachelineread.sv vendored
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@ -27,26 +27,27 @@
`include "wally-config.vh" `include "wally-config.vh"
module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)(
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,
input logic [LINELEN-1:0] ReadDataLine, input logic [LINELEN-1:0] ReadDataLine,
output logic [WORDLEN-1:0] ReadDataWord); output logic [WORDLEN-1:0] ReadDataWord
);
localparam WORDSPERLINE = LINELEN/MUXINTERVAL; localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
// pad is for icache. Muxing extends over the cacheline boundary.
localparam PADLEN = WORDLEN-MUXINTERVAL; localparam PADLEN = WORDLEN-MUXINTERVAL;
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; // pad is for icache. Muxing extends over the cacheline boundary.
logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad;
logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0];
if (PADLEN > 0) begin if (PADLEN > 0) begin
logic [PADLEN-1:0] Pad; assign ReadDataLinePad = {{PADLEN{1'b0}}, ReadDataLine};
assign Pad = '0;
assign ReadDataLinePad = {Pad, ReadDataLine};
end else assign ReadDataLinePad = ReadDataLine; end else assign ReadDataLinePad = ReadDataLine;
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)]; assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
end end
// variable input mux // variable input mux
assign ReadDataWord = ReadDataLineSets[PAdr]; assign ReadDataWord = ReadDataLineSets[PAdr];
endmodule endmodule