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Updating MMU signal Propagation

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Huda-10xe 2025-01-29 01:03:20 -08:00
parent c05de02384
commit 5684ae9441
4 changed files with 100 additions and 87 deletions
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78
config/rv32gc/coverage.svh
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@ -13,48 +13,44 @@
`define CLINT_BASE 64'h02000000 `define CLINT_BASE 64'h02000000
// Unprivileged extensions // Unprivileged extensions
`include "I_coverage.svh" // `include "I_coverage.svh"
`include "M_coverage.svh" // `include "M_coverage.svh"
`include "F_coverage.svh" // `include "F_coverage.svh"
`include "D_coverage.svh" // `include "D_coverage.svh"
`include "Zba_coverage.svh" // `include "Zba_coverage.svh"
`include "Zbb_coverage.svh" // `include "Zbb_coverage.svh"
`include "Zbc_coverage.svh" // `include "Zbc_coverage.svh"
`include "Zbs_coverage.svh" // `include "Zbs_coverage.svh"
`include "ZfaF_coverage.svh" // `include "ZfaF_coverage.svh"
`include "ZfaD_coverage.svh" // `include "ZfaD_coverage.svh"
`include "ZfaZfh_coverage.svh" // `include "ZfaZfh_coverage.svh"
`include "Zfh_coverage.svh" // `include "Zfh_coverage.svh"
`include "ZfhD_coverage.svh" // `include "ZfhD_coverage.svh"
// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled // `include "Zicond_coverage.svh"
`include "Zfhmin_coverage.svh" // `include "Zca_coverage.svh"
// Note: Zmmul is a subset of M, so usually only one or the other would be used. // `include "Zcb_coverage.svh"
`include "Zmmul_coverage.svh" // `include "ZcbM_coverage.svh"
`include "Zicond_coverage.svh" // `include "ZcbZbb_coverage.svh"
`include "Zca_coverage.svh" // `include "Zcf_coverage.svh"
`include "Zcb_coverage.svh" // `include "Zcd_coverage.svh"
`include "ZcbM_coverage.svh" // `include "Zicsr_coverage.svh"
`include "ZcbZbb_coverage.svh" // `include "Zbkb_coverage.svh"
`include "Zcf_coverage.svh" // `include "Zbkc_coverage.svh"
`include "Zcd_coverage.svh" // `include "Zbkx_coverage.svh"
`include "Zicsr_coverage.svh" // `include "Zknd_coverage.svh"
`include "Zbkb_coverage.svh" // `include "Zkne_coverage.svh"
`include "Zbkc_coverage.svh" // `include "Zknh_coverage.svh"
`include "Zbkx_coverage.svh" // `include "Zaamo_coverage.svh"
`include "Zknd_coverage.svh" // `include "Zalrsc_coverage.svh"
`include "Zkne_coverage.svh"
`include "Zknh_coverage.svh"
`include "Zaamo_coverage.svh"
`include "Zalrsc_coverage.svh"
// Privileged extensions // Privileged extensions
`include "ZicsrM_coverage.svh" // `include "ZicsrM_coverage.svh"
`include "ZicsrF_coverage.svh" // `include "ZicsrF_coverage.svh"
`include "ZicsrU_coverage.svh" // `include "ZicsrU_coverage.svh"
`include "RV32VM_coverage.svh" `include "RV32VM_coverage.svh"
`include "RV32VM_PMP_coverage.svh" `include "RV32VM_PMP_coverage.svh"
`include "EndianU_coverage.svh" // `include "EndianU_coverage.svh"
`include "EndianM_coverage.svh" // `include "EndianM_coverage.svh"
`include "EndianS_coverage.svh" // `include "EndianS_coverage.svh"
`include "ExceptionsM_coverage.svh" // `include "ExceptionsM_coverage.svh"
`include "ExceptionsZc_coverage.svh" // `include "ExceptionsZc_coverage.svh"

80
config/rv64gc/coverage.svh
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@ -13,50 +13,46 @@
`define CLINT_BASE 64'h02000000 `define CLINT_BASE 64'h02000000
// Unprivileged extensions // Unprivileged extensions
`include "I_coverage.svh" // `include "I_coverage.svh"
`include "M_coverage.svh" // `include "M_coverage.svh"
`include "F_coverage.svh" // `include "F_coverage.svh"
`include "D_coverage.svh" // `include "D_coverage.svh"
`include "Zba_coverage.svh" // `include "Zba_coverage.svh"
`include "Zbb_coverage.svh" // `include "Zbb_coverage.svh"
`include "Zbc_coverage.svh" // `include "Zbc_coverage.svh"
`include "Zbs_coverage.svh" // `include "Zbs_coverage.svh"
`include "ZfaF_coverage.svh" // `include "ZfaF_coverage.svh"
`include "ZfaD_coverage.svh" // `include "ZfaD_coverage.svh"
`include "ZfaZfh_coverage.svh" // `include "ZfaZfh_coverage.svh"
`include "ZfhD_coverage.svh" // `include "ZfhD_coverage.svh"
`include "Zfh_coverage.svh" // `include "Zfh_coverage.svh"
// Note: Zfhmin is a subset of Zfh, so usually only one or the other would be used. When Zfhmin and D are supported, ZfhD should also be enabled // `include "Zicond_coverage.svh"
`include "Zfhmin_coverage.svh" // `include "Zca_coverage.svh"
// Note: Zmmul is a subset of M, so usually only one or the other would be used. // `include "Zcb_coverage.svh"
`include "Zmmul_coverage.svh" // `include "ZcbM_coverage.svh"
`include "Zicond_coverage.svh" // `include "ZcbZbb_coverage.svh"
`include "Zca_coverage.svh" // `include "ZcbZba_coverage.svh"
`include "Zcb_coverage.svh" // `include "Zcd_coverage.svh"
`include "ZcbM_coverage.svh" // `include "Zicsr_coverage.svh"
`include "ZcbZbb_coverage.svh" // `include "Zbkb_coverage.svh"
`include "ZcbZba_coverage.svh" // `include "Zbkc_coverage.svh"
`include "Zcd_coverage.svh" // `include "Zbkx_coverage.svh"
`include "Zicsr_coverage.svh" // `include "Zknd_coverage.svh"
`include "Zbkb_coverage.svh" // `include "Zkne_coverage.svh"
`include "Zbkc_coverage.svh" // `include "Zknh_coverage.svh"
`include "Zbkx_coverage.svh" // `include "Zaamo_coverage.svh"
`include "Zknd_coverage.svh" // `include "Zalrsc_coverage.svh"
`include "Zkne_coverage.svh"
`include "Zknh_coverage.svh"
`include "Zaamo_coverage.svh"
`include "Zalrsc_coverage.svh"
// Privileged extensions // Privileged extensions
`include "RV64VM_coverage.svh" `include "RV64VM_coverage.svh"
`include "ZicsrM_coverage.svh" // `include "ZicsrM_coverage.svh"
`include "ZicsrF_coverage.svh" // `include "ZicsrF_coverage.svh"
`include "ZicsrU_coverage.svh" // `include "ZicsrU_coverage.svh"
`include "EndianU_coverage.svh" // `include "EndianU_coverage.svh"
`include "EndianM_coverage.svh" // `include "EndianM_coverage.svh"
`include "EndianS_coverage.svh" // `include "EndianS_coverage.svh"
`include "ExceptionsM_coverage.svh" // `include "ExceptionsM_coverage.svh"
`include "ExceptionsZc_coverage.svh" // `include "ExceptionsZc_coverage.svh"
// `include "RV64VM_PMP_coverage.svh" `include "RV64VM_PMP_coverage.svh"
// `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_VM_coverage.svh"
// `include "RV64CBO_PMP_coverage.svh" // `include "RV64CBO_PMP_coverage.svh"

21
sim/questa/wave.do
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@ -1,6 +1,27 @@
onerror {resume} onerror {resume}
quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -position insertpoint sim:/testbench/wallyTracer/PCF
add wave -position insertpoint sim:/testbench/wallyTracer/PCD
add wave -position insertpoint sim:/testbench/wallyTracer/PCE
add wave -position insertpoint sim:/testbench/wallyTracer/PCM
add wave -position insertpoint sim:/testbench/wallyTracer/PCW
add wave -position insertpoint sim:/testbench/wallyTracer/GatedStallW
add wave -position insertpoint sim:/testbench/dut/core/lsu/hptw/hptw/SelHPTW
add wave -position insertpoint sim:/testbench/wallyTracer/StallM
add wave -position insertpoint sim:/testbench/wallyTracer/StallW
add wave -position insertpoint sim:/testbench/wallyTracer/FlushW
add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iF
add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iD
add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iE
add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iM
add wave -position insertpoint sim:/testbench/wallyTracer/PTE_iW
add wave -position insertpoint sim:/testbench/wallyTracer/PageType_iM
add wave -position insertpoint sim:/testbench/wallyTracer/PageType_iW
add wave -position insertpoint sim:/testbench/wallyTracer/ExecuteAccessM
add wave -position insertpoint sim:/testbench/wallyTracer/ExecuteAccessW
add wave -position insertpoint sim:/testbench/rvvi/valid
add wave -position insertpoint sim:/testbench/rvvi/csr[0][0][834]
add wave -noupdate /testbench/clk add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset
add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/memfilename

8
testbench/common/wallyTracer.sv
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@ -364,25 +364,25 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
//for VM Verification //for VM Verification
flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU
flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IVAdrE, IVAdrM); //Virtual Address for IMMU
flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU
flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPAE, IPAM); //Physical Address for IMMU
flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU
flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPTEE, IPTEM); //PTE for IMMU
flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~StallD
flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~(StallM & ~SelHPTW), IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW
flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU // *** RT: possible bug SelHPTW probably should be ~GatedStallW