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Minor cosmetic update to fpu.sv

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This commit is contained in:
James E. Stine 2021-06-01 15:45:32 -04:00
parent 2eeb12c674
commit 564d7c4adb
1 changed files with 439 additions and 519 deletions
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98
wally-pipelined/src/fpu/fpu.sv
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@ -46,10 +46,6 @@ module fpu (
output logic IllegalFPUInstrD,
output logic [`XLEN-1:0] FPUResultW);
// control logic signal instantiation
logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
logic [2:0] FrmD, FrmE, FrmM, FrmW; // FP rounding mode
@ -163,8 +159,8 @@ module fpu (
// classify signals
logic [63:0] ClassResultE, ClassResultM, ClassResultW;
// other
logic [63:0] FPUResult64W, FPUResult64E; // 64-bit FPU result
// 64-bit FPU result
logic [63:0] FPUResult64W, FPUResult64E;
logic [4:0] FPUFlagsW;
// pipeline control logic
@ -180,28 +176,14 @@ module fpu (
localparam PipeClear = 1'b0;
localparam PipeEnable = 1'b1;
always_comb begin
PipeEnableDE = ~StallE;
PipeEnableEM = ~StallM;
PipeEnableMW = ~StallW;
PipeClearDE = FlushE;
PipeClearEM = FlushM;
PipeClearMW = FlushW;
end
//DECODE STAGE
// Hazard unit for FPU
@ -210,21 +192,12 @@ module fpu (
// top-level controller for FPU
fctrl ctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .*);
// regfile instantiation
FPregfile fpregfile (clk, reset, FWriteEnW,
InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
FPUResult64W,
FRD1D, FRD2D, FRD3D);
//*****************
// fpregfile D/E pipe registers
//*****************
@ -250,22 +223,8 @@ module fpu (
flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E);
flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
//EXECUTION STAGE
// input muxs for forwarding
mux4 #(64) FInput1Emux(FRD1E, FPUResult64W, FPUResult64E, SrcAM, FForwardInput1E, FInput1tmpE);
mux3 #(64) FInput2Emux(FRD2E, FPUResult64W, FPUResult64E, FForwardInput2E, FInput2E);
@ -296,21 +255,6 @@ module fpu (
// first and only instance of floating-point classify unit
fpuclassify fpuclass (.*);
//*****************
//fpregfile D/E pipe registers
//*****************
@ -410,13 +354,6 @@ module fpu (
//*****************
flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
//BEGIN MEMORY STAGE
assign FWriteDataM = FInput1M;
@ -429,17 +366,8 @@ module fpu (
fpuaddcvt2 fpadd2 (.*);
// second instance of two-stage floating-point comparator
fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM), .Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*);
fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM),
.Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*);
//*****************
// fma M/W pipe registers
@ -484,19 +412,11 @@ module fpu (
flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW);
flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
//*****************
// fpuclassify M/W pipe registers
//*****************
flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
//#########################################
// BEGIN WRITEBACK STAGE
//#########################################
@ -523,7 +443,6 @@ module fpu (
endcase
end
always_comb begin
case (FResultSelW)
// div/sqrt
@ -544,16 +463,17 @@ module fpu (
3'b111 : FPUResult64W = FLoadStoreResultW;
default : FPUResult64W = {64{1'bx}};
endcase
end
end // always_comb
// interface between XLEN size datapath and double-precision sized
// floating-point results
//
// define offsets for LSB zero extension or truncation
always_comb begin
// zero extension
FPUResultW = FPUResult64W[63:64-`XLEN];
SetFflagsM = FPUFlagsW;
end
endmodule
endmodule // fpu