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Minor cosmetic update to fpu.sv

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This commit is contained in:
James E. Stine 2021-06-01 15:45:32 -04:00
parent 2eeb12c674
commit 564d7c4adb
1 changed files with 439 additions and 519 deletions
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172
wally-pipelined/src/fpu/fpu.sv
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@ -46,11 +46,7 @@ module fpu (
output logic IllegalFPUInstrD, output logic IllegalFPUInstrD,
output logic [`XLEN-1:0] FPUResultW); output logic [`XLEN-1:0] FPUResultW);
// control logic signal instantiation
//control logic signal instantiation
logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
logic [2:0] FrmD, FrmE, FrmM, FrmW; // FP rounding mode logic [2:0] FrmD, FrmE, FrmM, FrmW; // FP rounding mode
logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
@ -142,7 +138,7 @@ module fpu (
logic [63:0] FAddResultM, FAddResultW; logic [63:0] FAddResultM, FAddResultW;
logic [4:0] FAddFlagsM, FAddFlagsW; logic [4:0] FAddFlagsM, FAddFlagsW;
//cmp signals // cmp signals
logic [7:0] WE, WM; logic [7:0] WE, WM;
logic [7:0] XE, XM; logic [7:0] XE, XM;
logic ANaNE, ANaNM; logic ANaNE, ANaNM;
@ -157,14 +153,14 @@ module fpu (
logic [63:0] SgnResultE, SgnResultM, SgnResultW; logic [63:0] SgnResultE, SgnResultM, SgnResultW;
logic [4:0] SgnFlagsE, SgnFlagsM, SgnFlagsW; logic [4:0] SgnFlagsE, SgnFlagsM, SgnFlagsW;
//instantiation of W stage regfile signals // instantiation of W stage regfile signals
logic [`XLEN-1:0] SrcAW; logic [`XLEN-1:0] SrcAW;
// classify signals // classify signals
logic [63:0] ClassResultE, ClassResultM, ClassResultW; logic [63:0] ClassResultE, ClassResultM, ClassResultW;
// other // 64-bit FPU result
logic [63:0] FPUResult64W, FPUResult64E; // 64-bit FPU result logic [63:0] FPUResult64W, FPUResult64E;
logic [4:0] FPUFlagsW; logic [4:0] FPUFlagsW;
// pipeline control logic // pipeline control logic
@ -175,65 +171,42 @@ module fpu (
logic PipeClearEM; logic PipeClearEM;
logic PipeClearMW; logic PipeClearMW;
//temporarily assign pipe clear and enable signals // temporarily assign pipe clear and enable signals
//to never flush & always be running // to never flush & always be running
localparam PipeClear = 1'b0; localparam PipeClear = 1'b0;
localparam PipeEnable = 1'b1; localparam PipeEnable = 1'b1;
always_comb begin always_comb begin
PipeEnableDE = ~StallE; PipeEnableDE = ~StallE;
PipeEnableEM = ~StallM; PipeEnableEM = ~StallM;
PipeEnableMW = ~StallW; PipeEnableMW = ~StallW;
PipeClearDE = FlushE; PipeClearDE = FlushE;
PipeClearEM = FlushM; PipeClearEM = FlushM;
PipeClearMW = FlushW; PipeClearMW = FlushW;
end end
//DECODE STAGE //DECODE STAGE
//Hazard unit for FPU // Hazard unit for FPU
fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*); fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*);
//top-level controller for FPU // top-level controller for FPU
fctrl ctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .*); fctrl ctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .*);
// regfile instantiation
//regfile instantiation
FPregfile fpregfile (clk, reset, FWriteEnW, FPregfile fpregfile (clk, reset, FWriteEnW,
InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW, InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
FPUResult64W, FPUResult64W,
FRD1D, FRD2D, FRD3D); FRD1D, FRD2D, FRD3D);
//***************** //*****************
//fpregfile D/E pipe registers // fpregfile D/E pipe registers
//***************** //*****************
flopenrc #(64) DEReg1(clk, reset, PipeClearDE, PipeEnableDE, FRD1D, FRD1E); flopenrc #(64) DEReg1(clk, reset, PipeClearDE, PipeEnableDE, FRD1D, FRD1E);
flopenrc #(64) DEReg2(clk, reset, PipeClearDE, PipeEnableDE, FRD2D, FRD2E); flopenrc #(64) DEReg2(clk, reset, PipeClearDE, PipeEnableDE, FRD2D, FRD2E);
flopenrc #(64) DEReg3(clk, reset, PipeClearDE, PipeEnableDE, FRD3D, FRD3E); flopenrc #(64) DEReg3(clk, reset, PipeClearDE, PipeEnableDE, FRD3D, FRD3E);
//***************** //*****************
//other D/E pipe registers // other D/E pipe registers
//***************** //*****************
flopenrc #(1) DEReg4(clk, reset, PipeClearDE, PipeEnableDE, FWriteEnD, FWriteEnE); flopenrc #(1) DEReg4(clk, reset, PipeClearDE, PipeEnableDE, FWriteEnD, FWriteEnE);
flopenrc #(3) DEReg5(clk, reset, PipeClearDE, PipeEnableDE, FResultSelD, FResultSelE); flopenrc #(3) DEReg5(clk, reset, PipeClearDE, PipeEnableDE, FResultSelD, FResultSelE);
@ -250,22 +223,8 @@ module fpu (
flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E); flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E);
flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE); flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
//EXECUTION STAGE //EXECUTION STAGE
// input muxs for forwarding // input muxs for forwarding
mux4 #(64) FInput1Emux(FRD1E, FPUResult64W, FPUResult64E, SrcAM, FForwardInput1E, FInput1tmpE); mux4 #(64) FInput1Emux(FRD1E, FPUResult64W, FPUResult64E, SrcAM, FForwardInput1E, FInput1tmpE);
mux3 #(64) FInput2Emux(FRD2E, FPUResult64W, FPUResult64E, FForwardInput2E, FInput2E); mux3 #(64) FInput2Emux(FRD2E, FPUResult64W, FPUResult64E, FForwardInput2E, FInput2E);
@ -274,7 +233,7 @@ module fpu (
fma1 fma1 (.*); fma1 fma1 (.*);
//first and only instance of floating-point divider // first and only instance of floating-point divider
logic fpdivClk; logic fpdivClk;
clockgater fpdivclkg(.E(FDivStartE), clockgater fpdivclkg(.E(FDivStartE),
@ -284,33 +243,18 @@ module fpu (
fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk)); fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk));
//first of two-stage instance of floating-point add/cvt unit // first of two-stage instance of floating-point add/cvt unit
fpuaddcvt1 fpadd1 (.*); fpuaddcvt1 fpadd1 (.*);
//first of two-stage instance of floating-point comparator // first of two-stage instance of floating-point comparator
fpucmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, FInput1E, FInput2E, FOpCtrlE[1:0]); fpucmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, FInput1E, FInput2E, FOpCtrlE[1:0]);
//first and only instance of floating-point sign converter // first and only instance of floating-point sign converter
fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*); fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*);
//first and only instance of floating-point classify unit // first and only instance of floating-point classify unit
fpuclassify fpuclass (.*); fpuclassify fpuclass (.*);
//***************** //*****************
//fpregfile D/E pipe registers //fpregfile D/E pipe registers
//***************** //*****************
@ -319,7 +263,7 @@ module fpu (
flopenrc #(64) EMFpReg3(clk, reset, PipeClearEM, PipeEnableEM, FInput3E, FInput3M); flopenrc #(64) EMFpReg3(clk, reset, PipeClearEM, PipeEnableEM, FInput3E, FInput3M);
//***************** //*****************
//fma E/M pipe registers // fma E/M pipe registers
//***************** //*****************
flopenrc #(13) EMRegFma1(clk, reset, PipeClearEM, PipeEnableEM, aligncntE, aligncntM); flopenrc #(13) EMRegFma1(clk, reset, PipeClearEM, PipeEnableEM, aligncntE, aligncntM);
flopenrc #(106) EMRegFma2(clk, reset, PipeClearEM, PipeEnableEM, rE, rM); flopenrc #(106) EMRegFma2(clk, reset, PipeClearEM, PipeEnableEM, rE, rM);
@ -348,7 +292,7 @@ module fpu (
flopenrc #(1) EMRegFma25(clk, reset, PipeClearEM, PipeEnableEM, prodinfE, prodinfM); flopenrc #(1) EMRegFma25(clk, reset, PipeClearEM, PipeEnableEM, prodinfE, prodinfM);
//***************** //*****************
//fpadd E/M pipe registers // fpadd E/M pipe registers
//***************** //*****************
flopenrc #(64) EMRegAdd1(clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM); flopenrc #(64) EMRegAdd1(clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM);
flopenrc #(64) EMRegAdd2(clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM); flopenrc #(64) EMRegAdd2(clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM);
@ -377,7 +321,7 @@ module fpu (
flopenrc #(1) EMRegAdd27(clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM); flopenrc #(1) EMRegAdd27(clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM);
//***************** //*****************
//fpcmp E/M pipe registers // fpcmp E/M pipe registers
//***************** //*****************
flopenrc #(8) EMRegCmp1(clk, reset, PipeClearEM, PipeEnableEM, WE, WM); flopenrc #(8) EMRegCmp1(clk, reset, PipeClearEM, PipeEnableEM, WE, WM);
flopenrc #(8) EMRegCmp2(clk, reset, PipeClearEM, PipeEnableEM, XE, XM); flopenrc #(8) EMRegCmp2(clk, reset, PipeClearEM, PipeEnableEM, XE, XM);
@ -386,15 +330,15 @@ module fpu (
flopenrc #(1) EMRegCmp5(clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM); flopenrc #(1) EMRegCmp5(clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM);
flopenrc #(1) EMRegCmp6(clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM); flopenrc #(1) EMRegCmp6(clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM);
//put this in for the event we want to delay fsgn - will otherwise bypass // put this in for the event we want to delay fsgn - will otherwise bypass
//***************** //*****************
//fpsgn E/M pipe registers // fpsgn E/M pipe registers
//***************** //*****************
flopenrc #(64) EMRegSgn2(clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM); flopenrc #(64) EMRegSgn2(clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM);
flopenrc #(5) EMRegSgn3(clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM); flopenrc #(5) EMRegSgn3(clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM);
//***************** //*****************
//other E/M pipe registers // other E/M pipe registers
//***************** //*****************
flopenrc #(1) EMReg1(clk, reset, PipeClearEM, PipeEnableEM, FWriteEnE, FWriteEnM); flopenrc #(1) EMReg1(clk, reset, PipeClearEM, PipeEnableEM, FWriteEnE, FWriteEnM);
flopenrc #(3) EMReg2(clk, reset, PipeClearEM, PipeEnableEM, FResultSelE, FResultSelM); flopenrc #(3) EMReg2(clk, reset, PipeClearEM, PipeEnableEM, FResultSelE, FResultSelM);
@ -406,17 +350,10 @@ module fpu (
flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM); flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
//***************** //*****************
//fpuclassify E/M pipe registers // fpuclassify E/M pipe registers
//***************** //*****************
flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM); flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
//BEGIN MEMORY STAGE //BEGIN MEMORY STAGE
assign FWriteDataM = FInput1M; assign FWriteDataM = FInput1M;
@ -425,56 +362,47 @@ module fpu (
fma2 fma2(.*); fma2 fma2(.*);
//second instance of two-stage floating-point add/cvt unit // second instance of two-stage floating-point add/cvt unit
fpuaddcvt2 fpadd2 (.*); fpuaddcvt2 fpadd2 (.*);
//second instance of two-stage floating-point comparator // second instance of two-stage floating-point comparator
fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM), .Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*); fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM),
.Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*);
//***************** //*****************
//fma M/W pipe registers // fma M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegFma1(clk, reset, PipeClearMW, PipeEnableMW, FmaResultM, FmaResultW); flopenrc #(64) MWRegFma1(clk, reset, PipeClearMW, PipeEnableMW, FmaResultM, FmaResultW);
flopenrc #(5) MWRegFma2(clk, reset, PipeClearMW, PipeEnableMW, FmaFlagsM, FmaFlagsW); flopenrc #(5) MWRegFma2(clk, reset, PipeClearMW, PipeEnableMW, FmaFlagsM, FmaFlagsW);
//***************** //*****************
//fpdiv M/W pipe registers // fpdiv M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegDiv1(clk, reset, PipeClearMW, PipeEnableMW, FDivResultM, FDivResultW); flopenrc #(64) MWRegDiv1(clk, reset, PipeClearMW, PipeEnableMW, FDivResultM, FDivResultW);
flopenrc #(5) MWRegDiv2(clk, reset, PipeClearMW, PipeEnableMW, FDivFlagsM, FDivFlagsW); flopenrc #(5) MWRegDiv2(clk, reset, PipeClearMW, PipeEnableMW, FDivFlagsM, FDivFlagsW);
flopenrc #(1) MWRegDiv3(clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW); flopenrc #(1) MWRegDiv3(clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW);
//***************** //*****************
//fpadd M/W pipe registers // fpadd M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegAdd1(clk, reset, PipeClearMW, PipeEnableMW, FAddResultM, FAddResultW); flopenrc #(64) MWRegAdd1(clk, reset, PipeClearMW, PipeEnableMW, FAddResultM, FAddResultW);
flopenrc #(5) MWRegAdd2(clk, reset, PipeClearMW, PipeEnableMW, FAddFlagsM, FAddFlagsW); flopenrc #(5) MWRegAdd2(clk, reset, PipeClearMW, PipeEnableMW, FAddFlagsM, FAddFlagsW);
//***************** //*****************
//fpcmp M/W pipe registers // fpcmp M/W pipe registers
//***************** //*****************
flopenrc #(1) MWRegCmp1(clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW); flopenrc #(1) MWRegCmp1(clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW);
flopenrc #(2) MWRegCmp2(clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW); flopenrc #(2) MWRegCmp2(clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW);
flopenrc #(64) MWRegCmp3(clk, reset, PipeClearMW, PipeEnableMW, FCmpResultM, FCmpResultW); flopenrc #(64) MWRegCmp3(clk, reset, PipeClearMW, PipeEnableMW, FCmpResultM, FCmpResultW);
//***************** //*****************
//fpsgn M/W pipe registers // fpsgn M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegSgn1(clk, reset, PipeClearMW, PipeEnableMW, SgnResultM, SgnResultW); flopenrc #(64) MWRegSgn1(clk, reset, PipeClearMW, PipeEnableMW, SgnResultM, SgnResultW);
flopenrc #(5) MWRegSgn2(clk, reset, PipeClearMW, PipeEnableMW, SgnFlagsM, SgnFlagsW); flopenrc #(5) MWRegSgn2(clk, reset, PipeClearMW, PipeEnableMW, SgnFlagsM, SgnFlagsW);
//***************** //*****************
//other M/W pipe registers // other M/W pipe registers
//***************** //*****************
flopenrc #(1) MWReg1(clk, reset, PipeClearMW, PipeEnableMW, FWriteEnM, FWriteEnW); flopenrc #(1) MWReg1(clk, reset, PipeClearMW, PipeEnableMW, FWriteEnM, FWriteEnW);
flopenrc #(3) MWReg2(clk, reset, PipeClearMW, PipeEnableMW, FResultSelM, FResultSelW); flopenrc #(3) MWReg2(clk, reset, PipeClearMW, PipeEnableMW, FResultSelM, FResultSelW);
@ -484,21 +412,13 @@ module fpu (
flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW); flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW);
flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW); flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
//***************** //*****************
//fpuclassify M/W pipe registers // fpuclassify M/W pipe registers
//***************** //*****************
flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW); flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
//######################################### //#########################################
//BEGIN WRITEBACK STAGE // BEGIN WRITEBACK STAGE
//######################################### //#########################################
always_comb begin always_comb begin
@ -523,7 +443,6 @@ module fpu (
endcase endcase
end end
always_comb begin always_comb begin
case (FResultSelW) case (FResultSelW)
// div/sqrt // div/sqrt
@ -544,16 +463,17 @@ module fpu (
3'b111 : FPUResult64W = FLoadStoreResultW; 3'b111 : FPUResult64W = FLoadStoreResultW;
default : FPUResult64W = {64{1'bx}}; default : FPUResult64W = {64{1'bx}};
endcase endcase
end end // always_comb
//interface between XLEN size datapath and double-precision sized
//floating-point results
//
//define offsets for LSB zero extension or truncation
always_comb begin
//zero extension // interface between XLEN size datapath and double-precision sized
// floating-point results
//
// define offsets for LSB zero extension or truncation
always_comb begin
// zero extension
FPUResultW = FPUResult64W[63:64-`XLEN]; FPUResultW = FPUResult64W[63:64-`XLEN];
SetFflagsM = FPUFlagsW; SetFflagsM = FPUFlagsW;
end end
endmodule
endmodule // fpu