Merge branch 'main' into fpga

2025-02-11 06:05:49 +00:00 · 2021-11-29 10:06:53 -06:00 · 2021-11-29 10:06:53 -06:00 · 5642918ead
commit 5642918ead
parent f4c221f20a d5cf6da6eb
659 changed files with 246423 additions and 10777 deletions
--- a/.gitignore
+++ b/.gitignore
@ -19,37 +19,19 @@ wlft*
 /imperas-riscv-tests/FunctionRadix.addr
 /imperas-riscv-tests/ProgramMap.txt
 /imperas-riscv-tests/logs
 /wally-pipelined/linux-testgen/qemu_output.txt
 /wally-pipelined/linux-testgen/qemu_in_gdb_format.txt
 *.o
 *.d
 testsBP/*/*/*.elf*
 testsBP/*/OBJ/*
 testsBP/*/*.a
-wally-pipelined/linux-testgen/linux-testvectors/*
+tests/linux-testgen/linux-testvectors/*
-wally-pipelined/linux-testgen/nohup*
+!tests/linux-testgen/linux-testvectors/tvCopier.py
-wally-pipelined/linux-testgen/x*
+!tests/linux-testgen/linux-testvectors/tvLinker.sh
-!wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py
+!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
-!wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh
+tests/linux-testgen/buildroot
-!wally-pipelined/linux-testgen/linux-testvectors/tvUnlinker.sh
+tests/linux-testgen/buildroot-image-output
-!wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs
+tests/linux-testgen/buildroot-config-src/main.config.old
-wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/*
+tests/linux-testgen/buildroot-config-src/linux.config.old
-!wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt
+tests/linux-testgen/buildroot-config-src/busybox.config.old
 wally-pipelined/linux-testgen/buildroot/
 wally-pipelined/linux-testgen/buildroot-image-output
 wally-pipelined/linux-testgen/buildroot-config-src/main.config.old
 wally-pipelined/linux-testgen/buildroot-config-src/linux.config.old
 wally-pipelined/linux-testgen/buildroot-config-src/busybox.config.old
 wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
 wally-pipelined/regression/logs
 /testsBP/fpga-test-dram/bin/blink-led
 /testsBP/fpga-test-dram/bin/blink-led.memfile
 /testsBP/fpga-test-dram/bin/blink-led.objdump
 /testsBP/fpga-test-dram/bin/blink-led.objdump.addr
 /testsBP/fpga-test-dram/bin/blink-led.objdump.lab
 /testsBP/fpga-test-sdc/bin/fpga-test-sdc
 /testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile
 /testsBP/fpga-test-sdc/bin/fpga-test-sdc.objdump
 /testsBP/fpga-test-sdc/bin/fpga-test-sdc.objdump.addr
 /testsBP/fpga-test-sdc/bin/fpga-test-sdc.objdump.lab
--- a/26
+++ b/26
@ -0,0 +1,26 @@
 make all: submodules other
 submodules: addins/riscv-isa-sim addins/riscv-arch-test
 	cd addins;git init; git submodule add https://github.com/riscv-non-isa/riscv-arch-test; git submodule add https://github.com/riscv-software-src/riscv-isa-sim
 	git submodule update --init --recursive
 other:
 	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F
 	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D
 	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
 	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D/Makefile.include
 ifneq ("$(wildcard $(addins/riscv-isa-sim/build/.*))",)
 else
 	mkdir addins/riscv-isa-sim/build
 endif
 	cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
 	make -C addins/riscv-isa-sim/
 	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
 	echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
 	make -C tests/wally-riscv-arch-test
 	make -C tests/wally-riscv-arch-test XLEN=32
 	cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf
 	make -C wally-pipelined/regression
--- a/README.md
+++ b/README.md
@ -8,12 +8,16 @@ To use Wally on Linux:
 ```
 git clone https://github.com/davidharrishmc/riscv-wally
 cd riscv-wally
-cd imperas-riscv-tests
+cd addins
-make
+*** can these clones be replaced with git submodule commands?
 cd ../addins
 git clone https://github.com/riscv-non-isa/riscv-arch-test
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 cd riscv-isa-sim
 *** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated
 cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
 <edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
 cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D
 <edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
 mkdir build
 cd build
 set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)
@ -28,6 +32,15 @@ edit Makefile.include
 make
 make XLEN=32
 exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
 cd ../../tests
 cd imperas-riscv-tests
 make
 cd ../wally-riscv-arch-test
 make
 make XLEN=32
 exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
 cd ../linux-testgen/linux-testvectors
 ./tvLinker.sh
 ```
 Notes:
--- a/benchmarks/riscv-coremark/.gitignore
+++ b/benchmarks/riscv-coremark/.gitignore
--- a/benchmarks/riscv-coremark/.gitmodules
+++ b/benchmarks/riscv-coremark/.gitmodules
--- a/benchmarks/riscv-coremark/LICENSE
+++ b/benchmarks/riscv-coremark/LICENSE
--- a/benchmarks/riscv-coremark/Makefile
+++ b/benchmarks/riscv-coremark/Makefile
@ -0,0 +1,16 @@
 work/coremark.bare.riscv.memfile: work/coremark.bare.riscv.objdump
 	exe2memfile.pl work/coremark.bare.riscv
 work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump 
 work/coremark.bare.riscv:
 	make -C coremark PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im"
 	mv coremark/coremark.bare.riscv work
 	#make -C ../../addins/coremark PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im"
 	#mv ../../addins/coremark/coremark.bare.riscv work
 .PHONY: clean
 clean:
 	rm -f work/*
--- a/benchmarks/riscv-coremark/coremark/LICENSE.md
+++ b/benchmarks/riscv-coremark/coremark/LICENSE.md
--- a/benchmarks/riscv-coremark/coremark/Makefile
+++ b/benchmarks/riscv-coremark/coremark/Makefile
--- a/benchmarks/riscv-coremark/coremark/README.md
+++ b/benchmarks/riscv-coremark/coremark/README.md
--- a/benchmarks/riscv-coremark/coremark/barebones/core_portme.c
+++ b/benchmarks/riscv-coremark/coremark/barebones/core_portme.c
--- a/benchmarks/riscv-coremark/coremark/barebones/core_portme.h
+++ b/benchmarks/riscv-coremark/coremark/barebones/core_portme.h
--- a/benchmarks/riscv-coremark/coremark/barebones/core_portme.mak
+++ b/benchmarks/riscv-coremark/coremark/barebones/core_portme.mak
--- a/benchmarks/riscv-coremark/coremark/barebones/cvt.c
+++ b/benchmarks/riscv-coremark/coremark/barebones/cvt.c
--- a/benchmarks/riscv-coremark/coremark/barebones/ee_printf.c
+++ b/benchmarks/riscv-coremark/coremark/barebones/ee_printf.c
--- a/benchmarks/riscv-coremark/coremark/core_list_join.c
+++ b/benchmarks/riscv-coremark/coremark/core_list_join.c
--- a/benchmarks/riscv-coremark/coremark/core_main.c
+++ b/benchmarks/riscv-coremark/coremark/core_main.c
--- a/benchmarks/riscv-coremark/coremark/core_matrix.c
+++ b/benchmarks/riscv-coremark/coremark/core_matrix.c
--- a/benchmarks/riscv-coremark/coremark/core_state.c
+++ b/benchmarks/riscv-coremark/coremark/core_state.c
--- a/benchmarks/riscv-coremark/coremark/core_util.c
+++ b/benchmarks/riscv-coremark/coremark/core_util.c
--- a/benchmarks/riscv-coremark/coremark/coremark.exe
+++ b/benchmarks/riscv-coremark/coremark/coremark.exe
--- a/benchmarks/riscv-coremark/coremark/coremark.h
+++ b/benchmarks/riscv-coremark/coremark/coremark.h
--- a/benchmarks/riscv-coremark/coremark/coremark.md5
+++ b/benchmarks/riscv-coremark/coremark/coremark.md5
--- a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.c
+++ b/benchmarks/riscv-coremark/coremark/cygwin/core_portme.c
--- a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.h
+++ b/benchmarks/riscv-coremark/coremark/cygwin/core_portme.h
--- a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.mak
+++ b/benchmarks/riscv-coremark/coremark/cygwin/core_portme.mak
--- a/benchmarks/riscv-coremark/coremark/docs/READM.md
+++ b/benchmarks/riscv-coremark/coremark/docs/READM.md
--- a/benchmarks/riscv-coremark/coremark/docs/balance_O0_joined.png
+++ b/benchmarks/riscv-coremark/coremark/docs/balance_O0_joined.png
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/PIC32/core_portme-mak.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/PIC32/core_portme-mak.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/core_list_join-c.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/core_list_join-c.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/core_main-c.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/core_main-c.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/core_matrix-c.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/core_matrix-c.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/core_state-c.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/core_state-c.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/core_util-c.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/core_util-c.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/coremark-h.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/coremark-h.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/docs/core_state.png
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/docs/core_state.png
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-c.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-c.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-h.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-h.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-mak.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-mak.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/readme-txt.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/readme-txt.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/files/release_notes-txt.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/files/release_notes-txt.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/BuildTargets.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/BuildTargets.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/Configuration.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/Configuration.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/Configurations.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/Configurations.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/Files.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/Files.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/Functions.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/Functions.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/General.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/General.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/General2.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/index/Types.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/Types.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/index/Variables.html
+++ b/benchmarks/riscv-coremark/coremark/docs/html/index/Variables.html
--- a/benchmarks/riscv-coremark/coremark/docs/html/javascript/main.js
+++ b/benchmarks/riscv-coremark/coremark/docs/html/javascript/main.js
--- a/benchmarks/riscv-coremark/coremark/docs/html/javascript/searchdata.js
+++ b/benchmarks/riscv-coremark/coremark/docs/html/javascript/searchdata.js
--- a/benchmarks/riscv-coremark/coremark/docs/html/search/BuildTargetsP.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationC.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationH.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationM.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationS.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationT.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationU.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationsH.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/FunctionsC.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/search/FunctionsG.html
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--- a/benchmarks/riscv-coremark/coremark/docs/html/styles/1.css
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