From 5634577a24f29af72c4db7510cb8bda1b94df030 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 26 Jun 2024 22:39:43 -0700 Subject: [PATCH] Remove verilator hack --- testbench/testbench.sv | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index be0422550..3661c6a98 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -385,14 +385,6 @@ module testbench; // and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end -`ifdef VERILATOR // this macro is defined when verilator is used - // Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is - // in the posedge clk block rather than a separate posedge Validate block. - // Until it is fixed, provide a silly posedge Validate block to keep Verilator happy. - // https://github.com/verilator/verilator/issues/4967 - end // restored - always @(posedge Validate) // added -`endif if(Validate) begin if (PrevPCZero) totalerrors = totalerrors + 1; // error if PC is stuck at zero if (TEST == "buildroot") @@ -445,10 +437,7 @@ module testbench; `endif end end -`ifndef VERILATOR - // Remove this when issue 4967 is resolved and the posedge Validate logic above is removed - end -`endif + end ////////////////////////////////////////////////////////////////////////////////