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Stripped write capaibilty out of rom_ahb

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David Harris 2022-08-24 17:23:08 -07:00
parent a131e1f17a
commit 562be633ab
3 changed files with 14 additions and 37 deletions
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40
pipelined/src/uncore/rom_ahb.sv
View File

@ -32,45 +32,23 @@
module rom_ahb #(parameter BASE=0, RANGE = 65535) ( module rom_ahb #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
input logic HSELRam, input logic HSELRom,
input logic [31:0] HADDR, input logic [31:0] HADDR,
input logic HWRITE,
input logic HREADY, input logic HREADY,
input logic [1:0] HTRANS, input logic [1:0] HTRANS,
input logic [`XLEN-1:0] HWDATA, output logic [`XLEN-1:0] HREADRom,
input logic [`XLEN/8-1:0] HWSTRB, output logic HRESPRom, HREADYRom
output logic [`XLEN-1:0] HREADRam,
output logic HRESPRam, HREADYRam
); );
localparam ADDR_WIDTH = $clog2(RANGE/8); localparam ADDR_WIDTH = $clog2(RANGE/8);
localparam OFFSET = $clog2(`XLEN/8); localparam OFFSET = $clog2(`XLEN/8);
logic [`XLEN/8-1:0] ByteMask; // Never stalls
logic [31:0] HADDRD, RamAddr; assign HREADYRom = 1'b1;
logic initTrans; assign HRESPRom = 0; // OK
logic memwrite, memwriteD, memread;
logic nextHREADYRam;
// a new AHB transactions starts when HTRANS requests a transaction, // single-ported ROM
// the peripheral is selected, and the previous transaction is completing brom1p1r #(ADDR_WIDTH, `XLEN)
assign initTrans = HREADY & HSELRam & HTRANS[1]; memory(.clk(HCLK), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
assign memwrite = initTrans & HWRITE;
assign memread = initTrans & ~HWRITE;
flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD);
flopenr #(32) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD);
// Stall on a read after a write because the RAM can't take both adddresses on the same cycle
assign nextHREADYRam = ~(memwriteD & memread);
flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
assign HRESPRam = 0; // OK
// On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
// single-ported RAM
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
endmodule endmodule

7
pipelined/src/uncore/uncore.sv
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@ -120,10 +120,9 @@ module uncore (
rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
bootrom( bootrom(
.HCLK, .HRESETn, .HCLK, .HRESETn,
.HSELRam(HSELBootRom), .HADDR, .HSELRom(HSELBootRom), .HADDR,
.HWRITE, .HREADY, .HTRANS, .HREADY, .HTRANS,
.HWDATA, .HWSTRB, .HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
.HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
end end
// memory-mapped I/O peripherals // memory-mapped I/O peripherals

4
pipelined/testbench/testbench-linux.sv
View File

@ -421,9 +421,9 @@ module testbench;
ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
// initialize bootrom // initialize bootrom
memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb"); memFile = $fopen({testvectorDir,"bootmem.bin"}, "rb");
readResult = $fread(dut.uncore.bootrom.bootrom.memory.RAM,memFile); readResult = $fread(dut.uncore.bootrom.bootrom.memory.ROM,memFile);
$fclose(memFile); $fclose(memFile);
// initialize RAM // initialize RAM and ROM
if (CHECKPOINT==0) if (CHECKPOINT==0)
memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
else else