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https://github.com/openhwgroup/cvw
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FSD and FLD imperas tests pass
This commit is contained in:
parent
142b02b30a
commit
55f22979ca
wally-pipelined
src
testbench
@ -15,6 +15,7 @@ module fctrl (
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output logic [2:0] FrmD,
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output logic [2:0] FrmD,
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output logic [1:0] FMemRWD,
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output logic [1:0] FMemRWD,
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output logic OutputInput2D,
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output logic OutputInput2D,
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output logic In2UsedD, In3UsedD,
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output logic FWriteIntD);
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output logic FWriteIntD);
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@ -55,50 +56,50 @@ module fctrl (
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//(or equivalent)
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//(or equivalent)
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always_comb begin
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always_comb begin
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//checks all but FMA/store/load
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//checks all but FMA/store/load
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IllegalFPUInstr2D = 0;
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IllegalFPUInstr2D = 0;
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if(OpD == 7'b1010011) begin
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if(OpD == 7'b1010011) begin
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casez(Funct7D)
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casez(Funct7D)
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//compare
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//compare
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7'b10100?? : FResultSelD = 3'b001;
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7'b10100?? : FResultSelD = 3'b001;
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//div/sqrt
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//div/sqrt
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7'b0?011?? : FResultSelD = 3'b000;
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7'b0?011?? : FResultSelD = 3'b000;
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//add/sub
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//add/sub
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7'b0000??? : FResultSelD = 3'b100;
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7'b0000??? : FResultSelD = 3'b100;
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//mult
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//mult
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7'b00010?? : FResultSelD = 3'b010;
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7'b00010?? : FResultSelD = 3'b010;
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//convert (not precision)
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//convert (not precision)
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7'b110?0?? : FResultSelD = 3'b100;
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7'b110?0?? : FResultSelD = 3'b100;
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//convert (precision)
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//convert (precision)
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7'b010000? : FResultSelD = 3'b100;
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7'b010000? : FResultSelD = 3'b100;
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//Min/Max
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//Min/Max
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7'b00101?? : FResultSelD = 3'b001;
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7'b00101?? : FResultSelD = 3'b001;
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//sign injection
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//sign injection
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7'b00100?? : FResultSelD = 3'b011;
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7'b00100?? : FResultSelD = 3'b011;
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//classify //only if funct3 = 001
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//classify //only if funct3 = 001
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7'b11100?? : if(Funct3D == 3'b001) FResultSelD = 3'b101;
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7'b11100?? : if(Funct3D == 3'b001) FResultSelD = 3'b101;
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//output ReadData1
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//output ReadData1
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else if (Funct7D[1] == 0) FResultSelD = 3'b111;
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else if (Funct7D[1] == 0) FResultSelD = 3'b111;
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//output SrcW
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//output SrcW
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7'b111100? : FResultSelD = 3'b110;
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7'b111100? : FResultSelD = 3'b110;
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default : begin FResultSelD = 3'b0; IllegalFPUInstr2D = 1'b1; end
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default : begin FResultSelD = 3'b0; IllegalFPUInstr2D = 1'b1; end
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endcase
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endcase
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end
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end
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//FMA/store/load
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//FMA/store/load
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else begin
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else begin
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case(OpD)
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case(OpD)
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//4 FMA instructions
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//4 FMA instructions
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7'b1000011 : FResultSelD = 3'b010;
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7'b1000011 : FResultSelD = 3'b010;
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7'b1000111 : FResultSelD = 3'b010;
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7'b1000111 : FResultSelD = 3'b010;
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7'b1001011 : FResultSelD = 3'b010;
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7'b1001011 : FResultSelD = 3'b010;
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7'b1001111 : FResultSelD = 3'b010;
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7'b1001111 : FResultSelD = 3'b010;
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//store
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//store
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7'b0100111 : FResultSelD = 3'b111;
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7'b0100111 : FResultSelD = 3'b111;
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//load
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//load
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7'b0000111 : FResultSelD = 3'b111;
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7'b0000111 : FResultSelD = 3'b111;
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default : begin FResultSelD = 3'b0; IllegalFPUInstr2D = 1'b1; end
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default : begin FResultSelD = 3'b0; IllegalFPUInstr2D = 1'b1; end
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endcase
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endcase
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end
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end
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end
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end
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assign OutputInput2D = OpD == 7'b0100111;
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assign OutputInput2D = OpD == 7'b0100111;
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@ -151,11 +152,12 @@ module fctrl (
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always_comb begin
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always_comb begin
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IllegalFPUInstr1D = 0;
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IllegalFPUInstr1D = 0;
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In3UsedD = 0;
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case (FResultSelD)
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case (FResultSelD)
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// div/sqrt
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// div/sqrt
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// fdiv = ???0
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// fdiv = ???0
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// fsqrt = ???1
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// fsqrt = ???1
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3'b000 : OpCtrlD = {3'b0, Funct7D[5]};
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3'b000 : begin OpCtrlD = {3'b0, Funct7D[5]}; In2UsedD = ~Funct7D[5]; end
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// cmp
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// cmp
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// fmin = ?100
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// fmin = ?100
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// fmax = ?101
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// fmax = ?101
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@ -163,7 +165,7 @@ module fctrl (
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// flt = ?001
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// flt = ?001
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// fle = ?011
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// fle = ?011
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// {?, is min or max, is eq or le, is lt or le}
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// {?, is min or max, is eq or le, is lt or le}
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3'b001 : OpCtrlD = {1'b0, Funct7D[2], ~Funct3D[0], ~(|Funct3D[2:1])};
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3'b001 : begin OpCtrlD = {1'b0, Funct7D[2], ~Funct3D[0], ~(|Funct3D[2:1])}; In2UsedD = 1'b1; end
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//fma/mult
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//fma/mult
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// fmadd = ?000
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// fmadd = ?000
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// fmsub = ?001
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// fmsub = ?001
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@ -171,12 +173,12 @@ module fctrl (
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// fnmsub = ?011
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// fnmsub = ?011
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// fmul = ?100
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// fmul = ?100
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// {?, is mul, is negitive, is sub}
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// {?, is mul, is negitive, is sub}
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3'b010 : OpCtrlD = {1'b0, OpD[4:2]};
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3'b010 : begin OpCtrlD = {1'b0, OpD[4:2]}; In2UsedD = 1'b1; In3UsedD = ~OpD[4]; end
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// sgn inj
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// sgn inj
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// fsgnj = ??00
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// fsgnj = ??00
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// fsgnjn = ??01
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// fsgnjn = ??01
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// fsgnjx = ??10
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// fsgnjx = ??10
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3'b011 : OpCtrlD = {2'b0, Funct3D[1:0]};
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3'b011 : begin OpCtrlD = {2'b0, Funct3D[1:0]}; In2UsedD = 1'b1; end
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// add/sub/cnvt
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// add/sub/cnvt
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// fadd = 0000
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// fadd = 0000
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// fsub = 0001
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// fsub = 0001
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@ -191,13 +193,13 @@ module fctrl (
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// fcvt.d.wu = 1111
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// fcvt.d.wu = 1111
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// fcvt.d.s = 1000
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// fcvt.d.s = 1000
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// { is double and not add/sub, is to/from int, is to int or float to double, is unsigned or sub
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// { is double and not add/sub, is to/from int, is to int or float to double, is unsigned or sub
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3'b100 : OpCtrlD = {Funct7D[0]&Funct7D[5], Funct7D[6], Funct7D[3] | (~Funct7D[6]&Funct7D[5]&~Funct7D[0]), Rs2D[0]|(Funct7D[2]&~Funct7D[5])};
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3'b100 : begin OpCtrlD = {Funct7D[0]&Funct7D[5], Funct7D[6], Funct7D[3] | (~Funct7D[6]&Funct7D[5]&~Funct7D[0]), Rs2D[0]|(Funct7D[2]&~Funct7D[5])}; In2UsedD = ~Funct7D[5]; end
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// classify {?, ?, ?, ?}
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// classify {?, ?, ?, ?}
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3'b101 : OpCtrlD = 4'b0;
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3'b101 : begin OpCtrlD = 4'b0; In2UsedD = 1'b0; end
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// output SrcAW
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// output SrcAW
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// fmv.w.x = ???0
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// fmv.w.x = ???0
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// fmv.w.d = ???1
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// fmv.w.d = ???1
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3'b110 : OpCtrlD = {3'b0, Funct7D[0]};
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3'b110 : begin OpCtrlD = {3'b0, Funct7D[0]}; In2UsedD = 1'b0; end
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// output Input1
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// output Input1
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// flw = ?000
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// flw = ?000
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// fld = ?001
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// fld = ?001
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@ -206,8 +208,8 @@ module fctrl (
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// fmv.x.w = ?100
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// fmv.x.w = ?100
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// fmv.d.w = ?101
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// fmv.d.w = ?101
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// {?, is mv, is store, is double or fcvt.d.w}
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// {?, is mv, is store, is double or fcvt.d.w}
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3'b111 : OpCtrlD = {1'b0, OpD[6:5], Funct3D[0] | (OpD[6]&Funct7D[0])};
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3'b111 : begin OpCtrlD = {1'b0, OpD[6:5], Funct3D[0] | (OpD[6]&Funct7D[0])}; In2UsedD = OpD[5]; end
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default : begin OpCtrlD = 4'b0; IllegalFPUInstr1D = 1'b1; end
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default : begin OpCtrlD = 4'b0; IllegalFPUInstr1D = 1'b1; In2UsedD = 1'b0; end
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endcase
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endcase
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end
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end
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@ -13,11 +13,12 @@ module fpu (
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input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg
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input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg
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input logic StallE, StallM, StallW,
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input logic StallE, StallM, StallW,
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input logic FlushE, FlushM, FlushW,
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input logic FlushE, FlushM, FlushW,
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input logic [`AHBW-1:0] HRDATA,
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input logic RegWriteD,
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input logic RegWriteD,
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output logic [4:0] SetFflagsM,
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output logic [4:0] SetFflagsM,
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output logic [31:0] FSROutW,
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output logic [31:0] FSROutW,
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output logic [1:0] FMemRWM,
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output logic [1:0] FMemRWM,
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output logic FStallE,
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output logic FStallD,
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output logic FWriteIntW,
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output logic FWriteIntW,
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output logic [`XLEN-1:0] FWriteDataM, // Integer input being written into fpreg
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output logic [`XLEN-1:0] FWriteDataM, // Integer input being written into fpreg
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output logic DivSqrtDoneE,
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output logic DivSqrtDoneE,
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@ -84,7 +85,7 @@ module fpu (
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logic DivBusyM;
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logic DivBusyM;
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logic [1:0] Input1MuxD, Input2MuxD;
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logic [1:0] Input1MuxD, Input2MuxD;
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logic Input3MuxD;
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logic Input3MuxD;
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logic In2UsedD, In3UsedD;
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//Hazard unit for FPU
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//Hazard unit for FPU
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fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*);
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fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*);
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@ -346,6 +347,7 @@ module fpu (
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//instantiation of M stage regfile signals
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//instantiation of M stage regfile signals
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logic [4:0] RdM;
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logic [4:0] RdM;
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logic [`XLEN-1:0] Input1M, Input2M, Input3M;
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logic [`XLEN-1:0] Input1M, Input2M, Input3M;
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logic [`XLEN-1:0] LoadStoreResultM;
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//instantiation of M stage add/cvt signals
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//instantiation of M stage add/cvt signals
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logic [63:0] AddResultM;
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logic [63:0] AddResultM;
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@ -485,6 +487,8 @@ module fpu (
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assign FWriteDataM = Input1M;
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assign FWriteDataM = Input1M;
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mux2 #(64) LoadStoreResultMux(HRDATA, Input1M, |OpCtrlM[2:1], LoadStoreResultM);
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fma2 fma2(.*);
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fma2 fma2(.*);
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//second instance of two-stage floating-point add/cvt unit
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//second instance of two-stage floating-point add/cvt unit
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@ -519,7 +523,7 @@ module fpu (
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logic [4:0] SgnFlagsW;
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logic [4:0] SgnFlagsW;
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//instantiation of W stage regfile signals
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//instantiation of W stage regfile signals
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logic [`XLEN-1:0] Input1W;
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logic [`XLEN-1:0] LoadStoreResultW;
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logic [`XLEN-1:0] SrcAW;
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logic [`XLEN-1:0] SrcAW;
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//instantiation of W stage add/cvt signals
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//instantiation of W stage add/cvt signals
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@ -576,7 +580,7 @@ module fpu (
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flopenrc #(1) MWReg3(clk, reset, PipeClearMW, PipeEnableMW, FmtM, FmtW);
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flopenrc #(1) MWReg3(clk, reset, PipeClearMW, PipeEnableMW, FmtM, FmtW);
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flopenrc #(5) MWReg4(clk, reset, PipeClearMW, PipeEnableMW, RdM, RdW);
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flopenrc #(5) MWReg4(clk, reset, PipeClearMW, PipeEnableMW, RdM, RdW);
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flopenrc #(`XLEN) MWReg5(clk, reset, PipeClearMW, PipeEnableMW, SrcAM, SrcAW);
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flopenrc #(`XLEN) MWReg5(clk, reset, PipeClearMW, PipeEnableMW, SrcAM, SrcAW);
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flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, Input1M, Input1W);
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flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, LoadStoreResultM, LoadStoreResultW);
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flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
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flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
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////END M/W PIPE
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////END M/W PIPE
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@ -628,6 +632,8 @@ module fpu (
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// ( (FResultSelW[0]) ? (FmaResultW) : ({62'b0,CmpFCCW}) )
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// ( (FResultSelW[0]) ? (FmaResultW) : ({62'b0,CmpFCCW}) )
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// : ( (FResultSelW[0]) ? (AddResultW) : (DivResultW) )
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// : ( (FResultSelW[0]) ? (AddResultW) : (DivResultW) )
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// );
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// );
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always_comb begin
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always_comb begin
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case (FResultSelW)
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case (FResultSelW)
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// div/sqrt
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// div/sqrt
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@ -644,8 +650,8 @@ module fpu (
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3'b101 : FPUResultDirW = ClassResultW;
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3'b101 : FPUResultDirW = ClassResultW;
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// output SrcAW
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// output SrcAW
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3'b110 : FPUResultDirW = SrcAW;
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3'b110 : FPUResultDirW = SrcAW;
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// output ReadData1
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// Load/Store/Move to FP-register
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3'b111 : FPUResultDirW = Input1W;
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3'b111 : FPUResultDirW = LoadStoreResultW;
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default : FPUResultDirW = {64{1'bx}};
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default : FPUResultDirW = {64{1'bx}};
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endcase
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endcase
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end
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end
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@ -32,8 +32,10 @@ module fpuhazard(
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input logic DivBusyM,
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input logic DivBusyM,
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input logic RegWriteD,
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input logic RegWriteD,
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input logic [2:0] FResultSelD, FResultSelE,
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input logic [2:0] FResultSelD, FResultSelE,
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input logic IllegalFPUInstrD,
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input logic In2UsedD, In3UsedD,
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// Stall outputs
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// Stall outputs
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output logic FStallE,
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output logic FStallD,
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output logic [1:0] Input1MuxD, Input2MuxD,
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output logic [1:0] Input1MuxD, Input2MuxD,
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output logic Input3MuxD
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output logic Input3MuxD
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);
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);
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@ -44,27 +46,28 @@ module fpuhazard(
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Input1MuxD = 2'b00;
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Input1MuxD = 2'b00;
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Input2MuxD = 2'b00;
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Input2MuxD = 2'b00;
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Input3MuxD = 1'b0;
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Input3MuxD = 1'b0;
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FStallE = DivBusyM;
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FStallD = DivBusyM;
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if (~IllegalFPUInstrD) begin
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if ((Adr1 == RdE) & (FRegWriteE | ((FResultSelE == 3'b110) & RegWriteD)))
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if ((Adr1 == RdE) & (FRegWriteE | ((FResultSelE == 3'b110) & RegWriteD)))
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if (FResultSelE == 3'b110) Input1MuxD = 2'b11; // choose SrcAM
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if (FResultSelE == 3'b110) Input1MuxD = 2'b11; // choose SrcAM
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else FStallE = 1'b1; // otherwise stall
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else FStallD = 1'b1; // otherwise stall
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else if ((Adr1 == RdM) & FRegWriteM) Input1MuxD = 2'b01; // choose FPUResultDirW
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else if ((Adr1 == RdW) & FRegWriteW) Input1MuxD = 2'b11; // choose FPUResultDirE
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else if ((Adr1 == RdM) & FRegWriteM) Input1MuxD = 2'b01; // choose FPUResultDirW
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if(In2UsedD)
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else if ((Adr1 == RdW) & FRegWriteW) Input1MuxD = 2'b11; // choose FPUResultDirE
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if ((Adr2 == RdE) & FRegWriteE) FStallD = 1'b1;
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else if ((Adr2 == RdM) & FRegWriteM) Input2MuxD = 2'b01; // choose FPUResultDirW
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else if ((Adr2 == RdW) & FRegWriteW) Input2MuxD = 2'b10; // choose FPUResultDirE
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else if ((Adr2 == RdE) & FRegWriteE) FStallE = 1'b1;//***add a signals saying whether input 1, 2 or 3 are used
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else if ((Adr2 == RdM) & FRegWriteM) Input2MuxD = 2'b01; // choose FPUResultDirW
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else if ((Adr2 == RdW) & FRegWriteW) Input2MuxD = 2'b10; // choose FPUResultDirE
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if(In3UsedD)
|
||||||
|
if ((Adr3 == RdE) & FRegWriteE) FStallD = 1'b1;
|
||||||
|
else if ((Adr3 == RdM) & FRegWriteM) FStallD = 1'b1;
|
||||||
|
else if ((Adr3 == RdW) & FRegWriteW) Input3MuxD = 1'b1; // choose FPUResultDirE
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
else if ((Adr3 == RdE) & FRegWriteE) FStallE = 1'b1;
|
|
||||||
else if ((Adr3 == RdM) & FRegWriteM) FStallE = 1'b1;
|
|
||||||
else if ((Adr3 == RdW) & FRegWriteW) Input3MuxD = 1'b1; // choose FPUResultDirE
|
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -32,7 +32,7 @@ module hazard(
|
|||||||
input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
|
||||||
input logic LoadStallD, MulDivStallD, CSRRdStallD,
|
input logic LoadStallD, MulDivStallD, CSRRdStallD,
|
||||||
input logic DataStall, ICacheStallF,
|
input logic DataStall, ICacheStallF,
|
||||||
input logic FStallE,
|
input logic FStallD,
|
||||||
input logic DivBusyE,
|
input logic DivBusyE,
|
||||||
// Stall & flush outputs
|
// Stall & flush outputs
|
||||||
output logic StallF, StallD, StallE, StallM, StallW,
|
output logic StallF, StallD, StallE, StallM, StallW,
|
||||||
@ -59,9 +59,9 @@ module hazard(
|
|||||||
assign BranchFlushDE = BPPredWrongE | RetM | TrapM;
|
assign BranchFlushDE = BPPredWrongE | RetM | TrapM;
|
||||||
|
|
||||||
assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE);
|
assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE);
|
||||||
assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD) & ~(BranchFlushDE); // stall in decode if instruction is a load/mul/csr dependent on previous
|
assign StallDCause = (LoadStallD | MulDivStallD | CSRRdStallD | FStallD) & ~(BranchFlushDE); // stall in decode if instruction is a load/mul/csr dependent on previous
|
||||||
// assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD; // stall in decode if instruction is a load/mul/csr dependent on previous
|
// assign StallDCause = LoadStallD | MulDivStallD | CSRRdStallD; // stall in decode if instruction is a load/mul/csr dependent on previous
|
||||||
assign StallECause = DivBusyE | FStallE;
|
assign StallECause = DivBusyE;
|
||||||
assign StallMCause = 0;
|
assign StallMCause = 0;
|
||||||
assign StallWCause = DataStall | ICacheStallF;
|
assign StallWCause = DataStall | ICacheStallF;
|
||||||
|
|
||||||
|
@ -97,7 +97,7 @@ module wallypipelinedhart (
|
|||||||
logic RegWriteD;
|
logic RegWriteD;
|
||||||
logic [`XLEN-1:0] FWriteDataM;
|
logic [`XLEN-1:0] FWriteDataM;
|
||||||
logic SquashSCW;
|
logic SquashSCW;
|
||||||
logic FStallE;
|
logic FStallD;
|
||||||
logic FWriteIntW;
|
logic FWriteIntW;
|
||||||
logic [31:0] FSROutW;
|
logic [31:0] FSROutW;
|
||||||
logic DivSqrtDoneE;
|
logic DivSqrtDoneE;
|
||||||
|
@ -134,7 +134,8 @@ string tests32f[] = '{
|
|||||||
// "rv64d/I-FCVT-WU-D-01", "2000",
|
// "rv64d/I-FCVT-WU-D-01", "2000",
|
||||||
// "rv64d/I-FDIV-D-01", "2000",
|
// "rv64d/I-FDIV-D-01", "2000",
|
||||||
// "rv64d/I-FEQ-D-01", "2000",
|
// "rv64d/I-FEQ-D-01", "2000",
|
||||||
"rv64d/I-FLD-D-01", "2000"
|
"rv64d/I-FSD-01", "2000",
|
||||||
|
"rv64d/I-FLD-01", "2420"
|
||||||
// "rv64d/I-FLE-D-01", "2000",
|
// "rv64d/I-FLE-D-01", "2000",
|
||||||
// "rv64d/I-FLT-D-01", "2000",
|
// "rv64d/I-FLT-D-01", "2000",
|
||||||
// "rv64d/I-FMADD-D-01", "2000",
|
// "rv64d/I-FMADD-D-01", "2000",
|
||||||
@ -145,7 +146,6 @@ string tests32f[] = '{
|
|||||||
// "rv64d/I-FMV-X-D-01", "2000",
|
// "rv64d/I-FMV-X-D-01", "2000",
|
||||||
// "rv64d/I-FNMADD-D-01", "2000",
|
// "rv64d/I-FNMADD-D-01", "2000",
|
||||||
// "rv64d/I-FNMSUB-D-01", "2000",
|
// "rv64d/I-FNMSUB-D-01", "2000",
|
||||||
//"rv64d/I-FSD-01", "2000"
|
|
||||||
// "rv64d/I-FSGNJ-D-01", "2000",
|
// "rv64d/I-FSGNJ-D-01", "2000",
|
||||||
// "rv64d/I-FSGNJN-D-01", "2000",
|
// "rv64d/I-FSGNJN-D-01", "2000",
|
||||||
// "rv64d/I-FSGNJX-D-01", "2000",
|
// "rv64d/I-FSGNJX-D-01", "2000",
|
||||||
|
Loading…
Reference in New Issue
Block a user