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Added counters to walk through d cache flush.

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This commit is contained in:
Ross Thompson 2021-09-16 17:12:51 -05:00
parent 4ca0c0ea7d
commit 55cbd957f0
1 changed files with 26 additions and 0 deletions
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26
wally-pipelined/src/cache/dcache.sv vendored
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@ -126,7 +126,16 @@ module dcache
logic [TAGLEN-1:0] VictimTag; logic [TAGLEN-1:0] VictimTag;
logic [INDEXLEN-1:0] FlushAdr; logic [INDEXLEN-1:0] FlushAdr;
logic [INDEXLEN-1:0] FlushAdrP1;
logic FlushAdrCntEn;
logic FlushAdrCntRst;
logic FlushAdrFlag;
logic [NUMWAYS-1:0] FlushWay; logic [NUMWAYS-1:0] FlushWay;
logic [NUMWAYS-1:0] NextFlushWay;
logic FlushWayCntEn;
logic FlushWayCntRst;
logic SelFlush; logic SelFlush;
logic AnyCPUReqM; logic AnyCPUReqM;
@ -299,6 +308,23 @@ module dcache
assign NextFetchCount = FetchCount + 1'b1; assign NextFetchCount = FetchCount + 1'b1;
// flush address and way generation.
flopenr #(INDEXLEN)
FlushAdrReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn),
.d(FlushAdrP1),
.q(FlushAdr));
flopenl #(NUMWAYS)
FlushWayReg(.clk,
.load(reset | FlushWayCntRst),
.en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}),
.d(NextFlushWay),
.q(FlushWay));
assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
// controller // controller