From 5c3118da9fd6c6688bd3f5880f805aa306d767d9 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Thu, 19 Sep 2024 07:24:27 -0700 Subject: [PATCH 01/10] Running VM COverage --- addins/cvw-arch-verif | 2 +- config/rv64gc/coverage.svh | 14 ++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 80cdee231..181354c2d 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 80cdee231f924b3045054594d4a7769e6eddcdcc +Subproject commit 181354c2d497cc0deab023ead4162648f38ace91 diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index ee811e922..7f68f7268 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -5,9 +5,11 @@ // This file is needed in the config subdirectory for each config supporting coverage. // It defines which extensions are enabled for that config. -`define COVER_RV64I -`define COVER_RV64M -`define COVER_RV64F -`include "coverage/RV64I_coverage.svh" -`include "coverage/RV64M_coverage.svh" -`include "coverage/RV64F_coverage.svh" +//`define COVER_RV64I +// `define COVER_RV64M +// `define COVER_RV64F +`define COVER_RV64VM +//`include "RV64I_coverage.svh" +// `include "coverage/RV64M_coverage.svh" +// `include "coverage/RV64F_coverage.svh" +`include "RV64VM_coverage.svh" From 36d74c745dcfe158066585e7c9954839e1a432b0 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 30 Sep 2024 01:55:20 -0700 Subject: [PATCH 02/10] discarding changes --- addins/cvw-arch-verif | 2 +- sim/questa/wally.do | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index cbcab51fb..854b3d701 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit cbcab51fb68859233c2377d76a7ef52f6118a53e +Subproject commit 854b3d701fc250051f2b8565d9a022d673352d3c diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 621fa1fbf..9af6fd727 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -194,7 +194,7 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -lint +nowarnRDGN -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286 +vlog -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282 -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals From 0817c691528713630d7629b2036ebc883c7a1f88 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 03:44:35 -0700 Subject: [PATCH 03/10] Adding priv coverage to ISACOV --- bin/regression-wally | 2 ++ config/rv64gc/coverage.svh | 5 +++++ sim/questa/wally.do | 4 ++-- testbench/common/wallyTracer.sv | 37 +++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 09f1e78ea..72d63dee8 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -414,6 +414,8 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) + elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index c89b116c9..cb24e1a45 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -8,5 +8,10 @@ `include "RV64I_coverage.svh" `include "RV64M_coverage.svh" `include "RV64F_coverage.svh" +// `include "RV64VM_coverage.svh" +// `include "RV64VM_PMP_coverage.svh" +// `include "RV64CBO_VM_coverage.svh" +// `include "RV64CBO_PMP_coverage.svh" +// `include "RV64Zicbom_coverage.svh" `include "RV64Zicond_coverage.svh" `include "RV64Zca_coverage.svh" diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 9af6fd727..ffb66d8bc 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -192,9 +192,9 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282 -suppress 2583 -suppress 7063,2596,13286 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 98969c37f..f8818032d 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -63,6 +63,16 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [11:0] CSRAdrM, CSRAdrW; logic wfiM; logic InterruptM, InterruptW; + + //For VM Verification + + logic [(P.XLEN-1):0] VAdrIM,VAdrDM,VAdrIW,VAdrDW; + logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; + logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; + logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; + logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; + logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; + assign clk = testbench.dut.clk; // assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet @@ -70,6 +80,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE; assign InstrValidM = testbench.dut.core.ieu.InstrValidM; assign InstrRawD = testbench.dut.core.ifu.InstrRawD; + assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; + assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; + assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; + assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; + assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; + assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; + assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; + assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE; + assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; + assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; + assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign PCNextF = testbench.dut.core.ifu.PCNextF; assign PCF = testbench.dut.core.ifu.PCF; assign PCD = testbench.dut.core.ifu.PCD; @@ -276,6 +297,22 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(12) CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); + //for VM Verification + flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); + flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); + flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); + flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); + flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); + flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); + flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); + flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); + flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD); + flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); + flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); + flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); + // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. From 24f97fa69649a9c1464808c7e2d930cb3547e72d Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 03:49:43 -0700 Subject: [PATCH 04/10] Adding DUT signals to the tracer for VM Coverage --- sim/questa/wally.do | 2 +- testbench/common/wallyTracer.sv | 22 ++++++++++++---------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index ffb66d8bc..6be1610d2 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -192,7 +192,7 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index f8818032d..d6ba31083 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -80,16 +80,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE; assign InstrValidM = testbench.dut.core.ieu.InstrValidM; assign InstrRawD = testbench.dut.core.ifu.InstrRawD; - assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; - assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; - assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; - assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; - assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; - assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; - assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; - assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE; - assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; - assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign PCNextF = testbench.dut.core.ifu.PCNextF; assign PCF = testbench.dut.core.ifu.PCF; @@ -113,6 +103,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL; assign wfiM = testbench.dut.core.priv.priv.wfiM; assign InterruptM = testbench.dut.core.priv.priv.InterruptM; + + //FOr VM Verification + assign VAdrIM = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; + assign VAdrDM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; + assign PAIM = testbench.dut.core.ifu.immu.immu.PhysicalAddress; + assign PADM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; + assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; + assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; + assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; + assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE; + assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; + assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; logic valid; From 896ff562a19f3daeacb4e4175c468d45e7dc2d82 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 03:51:11 -0700 Subject: [PATCH 05/10] adding privilege tests to regression --- bin/regression-wally | 1 - 1 file changed, 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 72d63dee8..9a9c57498 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -415,7 +415,6 @@ elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional c addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) - elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): From b77df83b597f141ca800322675c2b9956d53937c Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 03:52:36 -0700 Subject: [PATCH 06/10] Adding DUT signals to the tracer for VM Coverage --- testbench/common/wallyTracer.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index d6ba31083..83eeacf5f 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -80,7 +80,6 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE; assign InstrValidM = testbench.dut.core.ieu.InstrValidM; assign InstrRawD = testbench.dut.core.ifu.InstrRawD; - assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign PCNextF = testbench.dut.core.ifu.PCNextF; assign PCF = testbench.dut.core.ifu.PCF; assign PCD = testbench.dut.core.ifu.PCD; @@ -115,6 +114,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_iM = testbench.dut.core.ifu.immu.immu.PTE; assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; + assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + logic valid; From 9cd466a5f2c612bee1b870e0db5b2137118f32a6 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 03:57:31 -0700 Subject: [PATCH 07/10] Restoring cvw-arch-verif submodule --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 854b3d701..fc87c49be 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 854b3d701fc250051f2b8565d9a022d673352d3c +Subproject commit fc87c49be0f12378e5e16fc1ff260d4063f90bfb From fba5214a00aca6c44a8727056162cc2485e20578 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 04:34:09 -0700 Subject: [PATCH 08/10] Adding a separate folder for priv coverage files --- sim/questa/wally.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 6be1610d2..d147080f3 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -192,7 +192,7 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 From 58a534a9730c696e4cd7bbd2d9a87ee3d0d086bf Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 04:49:33 -0700 Subject: [PATCH 09/10] revertung submodule to its original --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index fc87c49be..e74441840 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit fc87c49be0f12378e5e16fc1ff260d4063f90bfb +Subproject commit e744418400cacf8c1366475827529a1d4e07702d From 61d24f7256d23c6f9b78e0038fa7d66182d7f7f8 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Mon, 7 Oct 2024 04:51:49 -0700 Subject: [PATCH 10/10] reverting submodule to its original --- addins/cvw-arch-verif | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index e74441840..80cdee231 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit e744418400cacf8c1366475827529a1d4e07702d +Subproject commit 80cdee231f924b3045054594d4a7769e6eddcdcc