diff --git a/bin/regression-wally b/bin/regression-wally
index 09f1e78ea..9a9c57498 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -414,6 +414,7 @@ if (args.ccov):  # only run RV64GC tests on Questa in code coverage mode
 elif (args.fcov):  # only run RV64GC tests on Questa in lockstep in functional coverage mode
     addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
     addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
+    addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
 elif (args.fcovrvvi):  # only run RV64GC tests on Questa in rvvi coverage mode
     addTests(tests64gc_nofp, coveragesim)
     if (args.fp):
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
index c89b116c9..cb24e1a45 100644
--- a/config/rv64gc/coverage.svh
+++ b/config/rv64gc/coverage.svh
@@ -8,5 +8,10 @@
 `include "RV64I_coverage.svh"
 `include "RV64M_coverage.svh"
 `include "RV64F_coverage.svh"
+// `include "RV64VM_coverage.svh"
+// `include "RV64VM_PMP_coverage.svh"
+// `include "RV64CBO_VM_coverage.svh"
+// `include "RV64CBO_PMP_coverage.svh"
+// `include "RV64Zicbom_coverage.svh"
 `include "RV64Zicond_coverage.svh"
 `include "RV64Zca_coverage.svh"
diff --git a/sim/questa/wally.do b/sim/questa/wally.do
index 621fa1fbf..d147080f3 100644
--- a/sim/questa/wally.do
+++ b/sim/questa/wally.do
@@ -192,9 +192,9 @@ if {$DEBUG > 0} {
 # suppress spurious warnngs about
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
+set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
 set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
-vlog -lint +nowarnRDGN -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286
+vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
index 98969c37f..83eeacf5f 100644
--- a/testbench/common/wallyTracer.sv
+++ b/testbench/common/wallyTracer.sv
@@ -63,6 +63,16 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [11:0] 					 CSRAdrM, CSRAdrW;
   logic                          wfiM;
   logic                          InterruptM, InterruptW;
+
+  //For VM Verification
+
+  logic [(P.XLEN-1):0]     VAdrIM,VAdrDM,VAdrIW,VAdrDW;
+  logic [(P.XLEN-1):0]     PTE_iM,PTE_dM,PTE_iW,PTE_dW;
+  logic [(P.PA_BITS-1):0]  PAIM,PADM,PAIW,PADW;
+  logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW;
+  logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
+  logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
+
     
   assign clk = testbench.dut.clk;
   //  assign InstrValidF = testbench.dut.core.ieu.InstrValidF;  // not needed yet
@@ -92,6 +102,20 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign STATUS_UXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
   assign wfiM           = testbench.dut.core.priv.priv.wfiM;
   assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;
+
+  //FOr VM Verification
+  assign VAdrIM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
+  assign VAdrDM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
+  assign PAIM           = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
+  assign PADM           = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
+  assign ReadAccessM    = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
+  assign WriteAccessM   = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
+  assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
+  assign PTE_iM         = testbench.dut.core.ifu.immu.immu.PTE;
+  assign PTE_dM         = testbench.dut.core.lsu.dmmu.dmmu.PTE;
+  assign PPN_iM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
+  assign PPN_dM         = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; 
+
   
 
   logic valid;
@@ -276,6 +300,22 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   flopenrc #(12)    CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW);
   flopenrc #(1)     CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
 
+  //for VM Verification
+  flopenrc #(P.XLEN)     VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW);
+  flopenrc #(P.XLEN)     VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW);
+  flopenrc #(P.PA_BITS)    PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW);
+  flopenrc #(P.PA_BITS)    PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW);
+  flopenrc #(P.XLEN)     PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW);
+  flopenrc #(P.XLEN)     PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW);
+  flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW);
+  flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW);
+  flopenrc #(1)  ReadAccessWReg    (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW);
+  flopenrc #(1)  WriteAccessWReg   (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW);
+  flopenrc #(1)  ExecuteAccessDReg (clk, reset, FlushE, ~StallE, ExecuteAccessF, ExecuteAccessD);
+  flopenrc #(1)  ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE);
+  flopenrc #(1)  ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM);
+  flopenrc #(1)  ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW);
+
   // Initially connecting the writeback stage signals, but may need to use M stage
   // and gate on ~FlushW.