diff --git a/wally-pipelined/src/regfile.sv b/wally-pipelined/src/regfile.sv
index 78238a823..738683efd 100644
--- a/wally-pipelined/src/regfile.sv
+++ b/wally-pipelined/src/regfile.sv
@@ -44,8 +44,8 @@ module regfile #(parameter XLEN=32) (
   // reset is intended for simulation only, not synthesis
     
   always_ff @(negedge clk or posedge reset)
-    if (reset) for(i=0; i<32; i++) rf[i] <= 0;
-    else if (we3 & (a3 != 0)) rf[a3] <= wd3;	
+    if (reset) for(i=1; i<32; i++) rf[i] <= 0;
+    else if (we3) rf[a3] <= wd3;	
 
   assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
   assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;