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https://github.com/openhwgroup/cvw
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added passing GPIO test to 64 bit tests
This commit is contained in:
Kip Macsai-Goren
parent
c6662933c4
commit
55627f40e2
@ -1828,7 +1828,7 @@ string imperas32f[] = '{
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`WALLYTEST,
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"rv64i_m/privilege/src/WALLY-periph-01.S",
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"rv64i_m/privilege/src/WALLY-clint-01.S",
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//"rv64i_m/privilege/src/WALLY-gpio-01.S",
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"rv64i_m/privilege/src/WALLY-gpio-01.S",
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"rv64i_m/privilege/src/WALLY-plic-01.S",
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"rv64i_m/privilege/src/WALLY-plic-s-01.S",
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"rv64i_m/privilege/src/WALLY-uart-01.S"
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@ -0,0 +1,81 @@
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00000000 # reset to zero tests: input_val
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00000000
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00000000 # input_en
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00000000
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00000000 # output_en
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00000000
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00000000 # output_val
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00000000
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00000000 # rise_ie
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00000000
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00000000 # fall_ie
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00000000
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00000000 # low_ie
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00000000
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00000000 # high_ie
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00000000
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00000000 # rise_ip
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00000000
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00000000 # fall_ip
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00000000
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00000000 # high_ip
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00000000
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ffffffff # low_ip
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ffffffff
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00000000 # out_xor
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00000000
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A5A5A5A5 # test output pins
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ffffffff
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5A5AFFFF
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00000000
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00000000 # test input enables
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00000000
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5A5A0000
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00000000
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A55A0000 # test XOR
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ffffffff
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A55A0000 # Test interrupt pending bits: high_ip
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ffffffff
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5AA5FFFF # low_ip
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00000000
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00000000 # rise_ip
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00000000
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00000000 # fall_ip
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00000000
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A4AA0000 # input_val
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ffffffff
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A5FA0000 # high_ip
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ffffffff
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5BF5FFFF # low_ip
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00000000
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00A00000 # rise_ip
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00000000
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01500000 # fall_ip
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00000000
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00000000 # MEIP
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00000000
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00000000 # Test interrupts can be enabled without being triggered: MIP = 0
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00000000
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00000000 # MIP = 0
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00000000
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00000000 # MIP = 0
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00000000
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00000000 # MIP = 0
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00000000
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00000800 # Test interrupts can be enabled and triggered: MEIP set from high_ie
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00000000
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00000000 # MEIP = 0
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00000000
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00000800 # MEIP set from low_ie
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00000000
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00000000 # MEIP = 0
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00000000
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00000800 # MEIP set from rise_ie
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00000000
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00000000 # MEIP = 0
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00000000
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00000800 # MEIP set from fall_ie
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00000000
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00000000 # MEIP = 0
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00000000
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@ -873,12 +873,12 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
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.equ PLIC_THRESH1, 0x0C201000 # Priority threshold for context 1 (supervisor mode)
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.equ PLIC_CLAIM1, 0x0C201004 # Claim/Complete register for context 1
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.4byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts
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.4byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts
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.4byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority
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.4byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority
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.4byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode
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.4byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode
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.8byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts
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.8byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts
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.8byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority
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.8byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority
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.8byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode
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.8byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode
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.endm
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.macro END_TESTS
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@ -0,0 +1,164 @@
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///////////////////////////////////////////
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//
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// WALLY-gpio
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//
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// Author: David_Harris@hmc.edu and Nicholas Lucio <nlucio@hmc.edu>
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//
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// Created 2022-06-16
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-64.h"
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RVTEST_ISA("RV64I")
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
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INIT_TESTS
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TRAP_HANDLER m
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j run_test_loop // begin test loop/table tests instead of executing inline code.
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INIT_TEST_TABLE
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END_TESTS
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TEST_STACK_AND_DATA
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.align 3
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test_cases:
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# ---------------------------------------------------------------------------------------------
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# Test Contents
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#
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# Here is where the actual tests are held, or rather, what the actual tests do.
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# each entry consists of 3 values that will be read in as follows:
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#
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# '.8byte [x28 Value], [x29 Value], [x30 value]'
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# or
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# '.8byte [address], [value], [test type]'
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#
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# The encoding for x30 test type values can be found in the test handler in the framework file
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#
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# ---------------------------------------------------------------------------------------------
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.equ GPIO, 0x10060000
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.equ input_val, (GPIO+0x00)
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.equ input_en, (GPIO+0x04)
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.equ output_en, (GPIO+0x08)
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.equ output_val, (GPIO+0x0C)
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.equ rise_ie, (GPIO+0x18)
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.equ rise_ip, (GPIO+0x1C)
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.equ fall_ie, (GPIO+0x20)
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.equ fall_ip, (GPIO+0x24)
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.equ high_ie, (GPIO+0x28)
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.equ high_ip, (GPIO+0x2C)
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.equ low_ie, (GPIO+0x30)
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.equ low_ip, (GPIO+0x34)
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.equ iof_en, (GPIO+0x38)
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.equ iof_sel, (GPIO+0x3C)
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.equ out_xor, (GPIO+0x40)
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# =========== Verify all registers reset to zero ===========
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.8byte input_val, 0x00000000, read32_test # input_val reset to zero
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.8byte input_en, 0x00000000, read32_test # input_en reset to zero
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.8byte output_en, 0x00000000, read32_test # output_en reset to zero
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.8byte output_val, 0x00000000, read32_test # output_val reset to zero
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.8byte rise_ie, 0x00000000, read32_test # rise_ie reset to zero
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.8byte fall_ie, 0x00000000, read32_test # fall_ie reset to zero
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.8byte high_ie, 0x00000000, read32_test # high_ie reset to zero
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.8byte low_ie, 0x00000000, read32_test # low_ie reset to zero
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.8byte rise_ip, 0x00000000, read32_test # rise_ip reset to zero
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.8byte fall_ip, 0x00000000, read32_test # fall_ip reset to zero
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.8byte high_ip, 0x00000000, read32_test # high_ip reset to zero
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.8byte low_ip, 0xffffffff, read32_test # low_ip reset to ones since all zeroes
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.8byte out_xor, 0x00000000, read32_test # out_xor reset to zero
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# =========== Test output and input pins ===========
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.8byte output_en, 0xFFFFFFFF, write32_test # enable all output pins
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.8byte output_val, 0xA5A5A5A5, write32_test # write alternating pattern to output pins
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.8byte input_en, 0xFFFFFFFF, write32_test # enable all input pins
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.8byte input_val, 0xA5A5A5A5, read32_test # read pattern from output pins
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.8byte output_val, 0x5A5AFFFF, write32_test # write different pattern to output pins
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.8byte input_val, 0x5A5AFFFF, read32_test # read different pattern from output pins
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# =========== Test input enables ===========
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.8byte input_en, 0x00000000, write32_test # disable all input pins
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.8byte input_val, 0x00000000, read32_test # read 0 since input pins are disabled
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.8byte input_en, 0xFFFF0000, write32_test # enable a few input pins
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.8byte input_val, 0x5A5A0000, read32_test # read part of pattern set above.
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# =========== Test XOR functionality ===========
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.8byte out_xor, 0xFF00FF00, write32_test # invert certain pin values
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.8byte input_val, 0xA55A0000, read32_test # read inverted pins and verify input enable is working
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# =========== Test Interrupt Pending bits ===========
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SETUP_PLIC
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.8byte low_ip, 0xFFFFFFFF, write32_test # clear pending low interrupts
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.8byte high_ip, 0xFFFFFFFF, write32_test # clear pending high interrupts
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.8byte rise_ip, 0xFFFFFFFF, write32_test # clear pending rise interrupts
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.8byte fall_ip, 0xFFFFFFFF, write32_test # clear pending fall interrupts
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.8byte high_ip, 0xA55A0000, read32_test # check pending high interrupts
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.8byte low_ip, 0x5AA5FFFF, read32_test # check pending low interrupts
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.8byte rise_ip, 0x00000000, read32_test # check pending rise interrupts
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.8byte fall_ip, 0x00000000, read32_test # check pending fall interrupts
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.8byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts
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.8byte input_val, 0xA4AA0000, read32_test # check new output matches expected output
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.8byte high_ip, 0xA5FA0000, read32_test # high interrupt pending
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.8byte low_ip, 0x5BF5FFFF, read32_test # low interrupt pending should be opposite high for enabled pins
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.8byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising)
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.8byte fall_ip, 0x01500000, read32_test # check for changed bits (falling)
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.8byte 0x0, 0x00000000, readmip_test # Check no external interrupt has been generated
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# =========== Test interrupts can be enabled without being triggered ===========
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.8byte high_ie, 0x00010000, write32_test # enable high interrupt on bit 16, no pending interrupt
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.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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.8byte low_ie, 0x00020000, write32_test # enable low interrupt on bit 17, no pending interrupt
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.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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.8byte rise_ie, 0x00010000, write32_test # enable rise interrupt on bit 16, no pending interrupt
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.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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.8byte fall_ie, 0x00010000, write32_test # enable fall interrupt on bit 16, no pending interrupt
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.8byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending
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# =========== Test interrupts can be enabled and triggered ===========
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.8byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending
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.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.8byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17
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.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.8byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.8byte low_ie, 0x00010000, write32_test # enable low interrupt on bit 16, which is pending
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.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.8byte low_ie, 0x00000000, write32_test # disable low interrupt on bit 16
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.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.8byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.8byte rise_ie, 0x00200000, write32_test # enable rise interrupt on bit 21, which is pending
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.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.8byte rise_ie, 0x00000000, write32_test # disable rise interrupt on bit 21, which is pending
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.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.8byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.8byte fall_ie, 0x01000000, write32_test # enable high interrupt on bit 24, which is pending
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.8byte 0x0, 0x00000800, readmip_test # MEIP should be raised
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.8byte fall_ie, 0x00000000, write32_test # disable high interrupt on bit 24, which is pending
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.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts
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.8byte 0x0, 0x00000000, readmip_test # MEIP should be released
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.8byte 0x0, 0x0, terminate_test # terminate tests
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