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Updated top level fpga file.

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This commit is contained in:
Ross Thompson 2022-11-18 11:10:45 -06:00
parent 840517a582
commit 55335d1db6
1 changed files with 96 additions and 96 deletions
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88
fpga/src/fpgaTop.v
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@ -60,7 +60,7 @@ module fpgaTop
output c0_ddr4_act_n, output c0_ddr4_act_n,
output [0 : 0] c0_ddr4_ck_c, output [0 : 0] c0_ddr4_ck_c,
output [0 : 0] c0_ddr4_ck_t output [0 : 0] c0_ddr4_ck_t
); );
wire CPUCLK; wire CPUCLK;
wire c0_ddr4_ui_clk_sync_rst; wire c0_ddr4_ui_clk_sync_rst;
@ -72,17 +72,17 @@ module fpgaTop
wire HCLKOpen; wire HCLKOpen;
wire HRESETnOpen; wire HRESETnOpen;
(* mark_debug = "true" *) wire [`AHBW-1:0] HRDATAEXT; wire [`AHBW-1:0] HRDATAEXT;
(* mark_debug = "true" *) wire HREADYEXT; wire HREADYEXT;
(* mark_debug = "true" *) wire HRESPEXT; wire HRESPEXT;
(* mark_debug = "true" *) wire HSELEXT; wire HSELEXT;
(* mark_debug = "true" *) wire [31:0] HADDR; wire [31:0] HADDR;
(* mark_debug = "true" *) wire [`AHBW-1:0] HWDATA; wire [`AHBW-1:0] HWDATA;
(* mark_debug = "true" *) wire HWRITE; wire HWRITE;
(* mark_debug = "true" *) wire [2:0] HSIZE; wire [2:0] HSIZE;
(* mark_debug = "true" *) wire [2:0] HBURST; wire [2:0] HBURST;
(* mark_debug = "true" *) wire [1:0] HTRANS; wire [1:0] HTRANS;
(* mark_debug = "true" *) wire HREADY; wire HREADY;
wire [3:0] HPROT; wire [3:0] HPROT;
wire HMASTLOCK; wire HMASTLOCK;
@ -94,41 +94,41 @@ module fpgaTop
wire SDCCmdOE; wire SDCCmdOE;
wire SDCCmdOut; wire SDCCmdOut;
(* mark_debug = "true" *) wire [3:0] m_axi_awid; wire [3:0] m_axi_awid;
(* mark_debug = "true" *) wire [7:0] m_axi_awlen; wire [7:0] m_axi_awlen;
(* mark_debug = "true" *) wire [2:0] m_axi_awsize; wire [2:0] m_axi_awsize;
(* mark_debug = "true" *) wire [1:0] m_axi_awburst; wire [1:0] m_axi_awburst;
(* mark_debug = "true" *) wire [3:0] m_axi_awcache; wire [3:0] m_axi_awcache;
(* mark_debug = "true" *) wire [31:0] m_axi_awaddr; wire [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot; wire [2:0] m_axi_awprot;
(* mark_debug = "true" *) wire m_axi_awvalid; wire m_axi_awvalid;
(* mark_debug = "true" *) wire m_axi_awready; wire m_axi_awready;
(* mark_debug = "true" *) wire m_axi_awlock; wire m_axi_awlock;
(* mark_debug = "true" *) wire [63:0] m_axi_wdata; wire [63:0] m_axi_wdata;
(* mark_debug = "true" *) wire [7:0] m_axi_wstrb; wire [7:0] m_axi_wstrb;
(* mark_debug = "true" *) wire m_axi_wlast; wire m_axi_wlast;
(* mark_debug = "true" *) wire m_axi_wvalid; wire m_axi_wvalid;
(* mark_debug = "true" *) wire m_axi_wready; wire m_axi_wready;
(* mark_debug = "true" *) wire [3:0] m_axi_bid; wire [3:0] m_axi_bid;
(* mark_debug = "true" *) wire [1:0] m_axi_bresp; wire [1:0] m_axi_bresp;
(* mark_debug = "true" *) wire m_axi_bvalid; wire m_axi_bvalid;
(* mark_debug = "true" *) wire m_axi_bready; wire m_axi_bready;
(* mark_debug = "true" *) wire [3:0] m_axi_arid; wire [3:0] m_axi_arid;
(* mark_debug = "true" *) wire [7:0] m_axi_arlen; wire [7:0] m_axi_arlen;
(* mark_debug = "true" *) wire [2:0] m_axi_arsize; wire [2:0] m_axi_arsize;
(* mark_debug = "true" *) wire [1:0] m_axi_arburst; wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot; wire [2:0] m_axi_arprot;
(* mark_debug = "true" *) wire [3:0] m_axi_arcache; wire [3:0] m_axi_arcache;
(* mark_debug = "true" *) wire m_axi_arvalid; wire m_axi_arvalid;
(* mark_debug = "true" *) wire [31:0] m_axi_araddr; wire [31:0] m_axi_araddr;
wire m_axi_arlock; wire m_axi_arlock;
(* mark_debug = "true" *) wire m_axi_arready; wire m_axi_arready;
(* mark_debug = "true" *) wire [3:0] m_axi_rid; wire [3:0] m_axi_rid;
(* mark_debug = "true" *) wire [63:0] m_axi_rdata; wire [63:0] m_axi_rdata;
(* mark_debug = "true" *) wire [1:0] m_axi_rresp; wire [1:0] m_axi_rresp;
(* mark_debug = "true" *) wire m_axi_rvalid; wire m_axi_rvalid;
(* mark_debug = "true" *) wire m_axi_rlast; wire m_axi_rlast;
(* mark_debug = "true" *) wire m_axi_rready; wire m_axi_rready;
wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arregion;
wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_arqos;