diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index bf943169c..b51e77e73 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -142,6 +142,8 @@ module dcache
 
   logic LRUWriteEn;
   
+  logic [NUMWAYS-1:0] VDWriteEnableWay;
+
   // Read Path CPU (IEU) side
 
   mux4 #(INDEXLEN)
@@ -167,7 +169,7 @@ module dcache
 		      .WAdr,
 		      .PAdr(MemPAdrM),
 		      .WriteEnable(SRAMWayWriteEnable),
-		      .VDWriteEnable,		      
+		      .VDWriteEnable(VDWriteEnableWay),
 		      .WriteWordEnable(SRAMWordEnable),
 		      .TagWriteEnable(SRAMBlockWayWriteEnableM), 
 		      .WriteData(SRAMWriteData),
@@ -329,6 +331,8 @@ module dcache
 	      .d(NextFlushWay),
 	      .q(FlushWay));
 
+  assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};  
+
   assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
 
   assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];