diff --git a/bin/regression-wally b/bin/regression-wally index f85800bba..add2bd24a 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -423,6 +423,7 @@ def main(): """Run the tests and count the failures""" global configs, coverage os.chdir(regressionDir) + os.system('rm -rf questa/wkdir') for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]: try: os.mkdir(d) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 44ff08aee..cf2ff9cce 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -112,7 +112,6 @@ make install # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g -sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g cd $RISCV git clone https://github.com/verilator/verilator # Only first time # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 5e3a2e419..44bf77eac 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -110,20 +110,10 @@ localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : B localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN)); localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1)); -// size of FMA output +// size of FMA output in U(NF+4).(3NF+2) format localparam FMALEN = 3*NF + 6; // NORMSHIFTSIZE is the bits out of the normalization shifter -// RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75 -// RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89 -// RV64D: max(84+52+1, 64+52+2, 3*52+6) = 162 -// *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing for fcvt.lu.s -// with CVTLEN+NF+1. Changing to CVTLEN+NF+1+2 fixes failures -// This same failure occurred for any test with IDIV_ON_FPU = 0, FLEN=32, XLEN=64 -// because NORMSHIFTSZ becomes limited by convert rather than divider -// The two extra bits are necessary because shiftcorrection dropped them for fcvt. -// May be possible to remove these two bits by modifying shiftcorrection -//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (FMALEN + 2)); localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2)); localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ) diff --git a/sim/verilator/wrapper.c b/sim/verilator/wrapper.c index 6589a3848..572acaa55 100644 --- a/sim/verilator/wrapper.c +++ b/sim/verilator/wrapper.c @@ -3,5 +3,9 @@ #include "Vtestbench__Dpi.h" const char *getenvval(const char *pszName) { + const char *pszValue = getenv(pszName); + if (pszValue == NULL) { + return ""; + } return ((const char *) getenv(pszName)); } \ No newline at end of file diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 53d43a6b3..3569a92e3 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -7,7 +7,7 @@ // // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 3cbadd530..cb111eade 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -7,7 +7,7 @@ // // Purpose: Implements Pseudo LRU. Tested for Powers of 2. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index d3cff2e96..64084f863 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for the cache fsm // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 41e620547..7406ebd83 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -7,7 +7,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 95920ec7e..3e9718c27 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -7,7 +7,7 @@ // // Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes. // -// Documentation: RISC-V System on Chip Design Chapter 7 +// Documentation: RISC-V System on Chip Design // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index f033b40cc..59d492ac4 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -7,7 +7,7 @@ // // Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions. // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -114,11 +114,12 @@ module ahbcacheinterface import cvw::*; #( .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec - // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. - // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - - flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); + if (READ_ONLY_CACHE) begin + assign HWSTRB = '0; + end else begin // compute byte mask for AHB transaction based on size and address. AHBW may be different than LLEN + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); + end buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 8852b52c3..a9bf8f497 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -7,7 +7,7 @@ // // Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ). // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index b0f28966e..5f39e1602 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for cache to AHB bus interface // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 11ba896e4..8aa640673 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -7,7 +7,7 @@ // // Purpose: Simple NON_SEQ (no burst) AHB controller. // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index 67e4795a6..97ea0d5b4 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -11,7 +11,7 @@ // Connects core to peripherals and I/O pins on SOC // Bus width presently matches XLEN // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 1b6c0a1fa..2eec7db58 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -11,7 +11,7 @@ // Connects core to peripherals and I/O pins on SOC // Bus width presently matches XLEN // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -110,7 +110,7 @@ module ebu import cvw::*; #(parameter cvw_t P) ( .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY)); - // output mux //*** switch to structural implementation + // output mux assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0; assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0; assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 571bdcc63..daf3da1e8 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -8,7 +8,7 @@ // Purpose: Arbitrates requests from instruction and data streams // LSU has priority. // -// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fclassify.sv b/src/fpu/fclassify.sv index f35f71869..6f52b0eae 100644 --- a/src/fpu/fclassify.sv +++ b/src/fpu/fclassify.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point classify unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 0944090fc..d1baac3b8 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point comparison unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index d8c1fe1d7..4f1bf042b 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -6,7 +6,7 @@ // // Purpose: floating-point control unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index ad3a2f602..90e8d7a23 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point conversions of configurable size // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // Int component of the Wally configurable RISC-V project. // @@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // shifter /////////////////////////////////////////////////////////////////////////// - // kill the shift if it's negative + // kill the shift if it is negative // select the amount to shift by // fp -> int: // - shift left by CalcExp - essentially shifting until the unbiased exponent = 0 @@ -201,10 +201,10 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // - shift left by LeadingZeros - to shift till the result is normalized // - only shift fp -> fp if the intital value is subnormal // - this is a problem because the input to the lzc was the fraction rather than the mantissa - // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? + // - rather have a few and-gates than an extra bit in the priority encoder??? always_comb if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}}; - else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0]; + else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0]; else ShiftAmt = LeadingZeros; /////////////////////////////////////////////////////////////////////////// diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index dba69267a..578996315 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -6,7 +6,7 @@ // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index 9e2489eb3..6a44b0ced 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -6,7 +6,7 @@ // // Purpose: Determine number of cycles for divsqrt // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 03d144263..058a3d17b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Exponent caclulation for divide and square root // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index bc9dce536..799ded999 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 F Addend Generator // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index a04523e58..90af95643 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 F Addend Generator // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8975edeb6..4e05b5e58 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -6,7 +6,7 @@ // // Purpose: divsqrt state machine for multi-cycle operations // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 4bfcebcd1..dc6b0057a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -6,7 +6,7 @@ // // Purpose: k stages of divsqrt logic, plus registers // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -44,7 +44,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) ( logic [P.DIVb+3:0] WCNext[P.DIVCOPIES-1:0]; // Q4.DIVb logic [P.DIVb+3:0] WS[P.DIVCOPIES:0]; // Q4.DIVb logic [P.DIVb+3:0] WC[P.DIVCOPIES:0]; // Q4.DIVb - logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb // *** probably Q not U. See Table 16.26 notes + logic [P.DIVb:0] U[P.DIVCOPIES:0]; // U1.DIVb logic [P.DIVb:0] UM[P.DIVCOPIES:0]; // U1.DIVb logic [P.DIVb:0] UNext[P.DIVCOPIES-1:0]; // U1.DIVb logic [P.DIVb:0] UMNext[P.DIVCOPIES-1:0]; // U1.DIVb diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index c3954bc0a..5bfb11b56 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -6,7 +6,7 @@ // // Purpose: Divide/Square root postprocessing // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 802ac92dc..1f668911a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -6,7 +6,7 @@ // // Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -222,7 +222,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic RemOpE; /* verilator lint_off WIDTH */ - assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. rn = Cycles * r * k - r ***explain + assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. n = (Cycles * k - 1) assign IntRemNormShiftE = mE + (P.DIVb-(P.XLEN-1)); // m + b - (N-1) for remainder normalization shift /* verilator lint_on WIDTH */ assign RemOpE = Funct3E[1]; diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index c3d6e210c..fa13cadeb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -6,7 +6,7 @@ // // Purpose: radix-2 divsqrt recurrence stage // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index 856273a5e..551a358c4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -6,7 +6,7 @@ // // Purpose: radix-4 divsqrt recurrence stage // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -52,7 +52,7 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( // Digit Selection logic assign j0 = ~C[P.DIVb+1]; // first step of R digit selection: C = 00...0 - assign j1 = C[P.DIVb] & ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; *** could simplify to ~C[P.DIVb-1] because j=0 case takes priority + assign j1 = ~C[P.DIVb-1]; // second step of R digit selection: C = 1100...0; simplified from C[P.DIVb] & ~C[P.DIVb-1] because j=0 case takes priority assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1 assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 55810665b..db858cb0b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 unified on-the-fly converter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index 5a802934e..3d842f9a8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 4 unified on-the-fly converter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv index 2d4cd5e48..193231eea 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -6,7 +6,7 @@ // // Purpose: Radix 2 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv index 610b79395..840215c28 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -6,7 +6,7 @@ // // Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index fd1092497..606b1202f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -6,7 +6,7 @@ // // Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -95,7 +95,7 @@ module fdivsqrtuslc4cmp ( // Choose A for current operation always_comb if (SqrtE) begin - if (Smsbs[4]) A = 3'b111; // for S = 1.0000 *** can we optimize away this case? + if (Smsbs[4]) A = 3'b111; // for S = 1.0000 else A = Smsbs[2:0]; end else A = Dmsbs; @@ -108,7 +108,7 @@ module fdivsqrtuslc4cmp ( /* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000 assign mk0 = -mk1; - assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path + assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table */ // Compare residual W to selection constants to choose digit @@ -117,5 +117,5 @@ module fdivsqrtuslc4cmp ( else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1 else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0 else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1 - else udigit = 4'b0001; // choose -2 + else udigit = 4'b0001; // choose -2 endmodule diff --git a/src/fpu/fhazard.sv b/src/fpu/fhazard.sv index e68934294..c31324ad1 100644 --- a/src/fpu/fhazard.sv +++ b/src/fpu/fhazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine forwarding, stalls and flushes for the FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fli.sv b/src/fpu/fli.sv index cf3b736d7..349189f33 100644 --- a/src/fpu/fli.sv +++ b/src/fpu/fli.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point float immediate // -// Documentation: RISC-V System on Chip Design Chapter 16 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv index 8bf4d4cbb..36d4a0ad5 100644 --- a/src/fpu/fma/fma.sv +++ b/src/fpu/fma/fma.sv @@ -6,7 +6,7 @@ // // Purpose: Floating point multiply-accumulate of configurable size // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv index 995494f2c..4942f9d9f 100644 --- a/src/fpu/fma/fmaadd.sv +++ b/src/fpu/fma/fmaadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA significand adder // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv index c6f0afebc..292472f7f 100644 --- a/src/fpu/fma/fmaalign.sv +++ b/src/fpu/fma/fmaalign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA alginment shift // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv index 06ac7e290..4ad254f79 100644 --- a/src/fpu/fma/fmaexpadd.sv +++ b/src/fpu/fma/fmaexpadd.sv @@ -6,7 +6,7 @@ // // Purpose: FMA exponent addition // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 01439f4d1..417b9de28 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -6,7 +6,7 @@ // // Purpose: Leading Zero Anticipator // -// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14) +// Documentation: RISC-V System on Chip Design // See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] // // A component of the CORE-V-WALLY configurable RISC-V project. diff --git a/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv index 8ce492f03..ea0ea2238 100644 --- a/src/fpu/fma/fmamult.sv +++ b/src/fpu/fma/fmamult.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Significand Multiplier // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv index 891c28746..8220f0aad 100644 --- a/src/fpu/fma/fmasign.sv +++ b/src/fpu/fma/fmasign.sv @@ -6,7 +6,7 @@ // // Purpose: FMA Sign Logic // -// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fmtparams.sv b/src/fpu/fmtparams.sv index d83dfd782..ad2dcfa4d 100644 --- a/src/fpu/fmtparams.sv +++ b/src/fpu/fmtparams.sv @@ -7,7 +7,7 @@ // // Purpose: Look up bias of exponent and number of fractional bits for the selected format // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index ba986dadc..122888509 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -6,7 +6,7 @@ // // Purpose: Floating Point Unit Top-Level Interface // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -218,7 +218,6 @@ module fpu import cvw::*; #(parameter cvw_t P) ( {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}, {2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10); - // ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10); mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index e907875a2..40933de17 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -6,7 +6,7 @@ // // Purpose: 3R1W 4-port register file for FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fround.sv b/src/fpu/fround.sv index d905618ba..bf4a4f7ad 100644 --- a/src/fpu/fround.sv +++ b/src/fpu/fround.sv @@ -6,7 +6,7 @@ // // Purpose: Floating-point round to integer for Zfa // -// Documentation: RISC-V System on Chip Design Chapter 16 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 4fe03522b..68e2eb493 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -6,7 +6,7 @@ // // Purpose: FPU Sign Injection instructions // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/packoutput.sv b/src/fpu/packoutput.sv index c9a500700..a81527e01 100644 --- a/src/fpu/packoutput.sv +++ b/src/fpu/packoutput.sv @@ -7,7 +7,7 @@ // // Purpose: Pack the output of the FPU // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv index 19993a996..84f5120a0 100644 --- a/src/fpu/postproc/cvtshiftcalc.sv +++ b/src/fpu/postproc/cvtshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Conversion shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv index d45afeea6..d46b58f35 100644 --- a/src/fpu/postproc/divshiftcalc.sv +++ b/src/fpu/postproc/divshiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: Division shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv index cb16cc2a1..be28a490c 100644 --- a/src/fpu/postproc/flags.sv +++ b/src/fpu/postproc/flags.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing flag calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv index cf334aa9b..22c354e30 100644 --- a/src/fpu/postproc/fmashiftcalc.sv +++ b/src/fpu/postproc/fmashiftcalc.sv @@ -6,7 +6,7 @@ // // Purpose: FMA shift calculation // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index 5ca848b0b..b9cb038a4 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -6,7 +6,7 @@ // // Purpose: Negate integer result // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv index f235d4d5b..d0a14cbfd 100644 --- a/src/fpu/postproc/normshift.sv +++ b/src/fpu/postproc/normshift.sv @@ -6,7 +6,7 @@ // // Purpose: normalization shifter // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv index 2db03cb16..f4af9d440 100644 --- a/src/fpu/postproc/postprocess.sv +++ b/src/fpu/postproc/postprocess.sv @@ -6,7 +6,7 @@ // // Purpose: Post-Processing: normalization, rounding, sign, flags, special cases // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -157,11 +157,11 @@ module postprocess import cvw::*; #(parameter cvw_t P) ( end 2'b00: begin // cvt ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt}; - ShiftIn = {CvtShiftIn, {P.NORMSHIFTSZ-P.CVTLEN-P.NF-1{1'b0}}}; + ShiftIn = {CvtShiftIn, {P.NORMSHIFTSZ-(P.CVTLEN+P.NF+1){1'b0}}}; end 2'b01: begin //divsqrt ShiftAmt = DivShiftAmt; - ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}}; + ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-(P.DIVb+1+P.NF){1'b0}}}; end default: begin ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; diff --git a/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv index 69f25a2b0..9425ec7ee 100644 --- a/src/fpu/postproc/resultsign.sv +++ b/src/fpu/postproc/resultsign.sv @@ -6,7 +6,7 @@ // // Purpose: calculating the result's sign // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index c99d5185c..4c6d251fb 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -6,7 +6,7 @@ // // Purpose: Rounder // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv index 7eedc5eba..fe422b98c 100644 --- a/src/fpu/postproc/roundsign.sv +++ b/src/fpu/postproc/roundsign.sv @@ -6,7 +6,7 @@ // // Purpose: Sign calculation for rounding // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv index ad811a747..03ec66a72 100644 --- a/src/fpu/postproc/shiftcorrection.sv +++ b/src/fpu/postproc/shiftcorrection.sv @@ -6,7 +6,7 @@ // // Purpose: shift correction // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -51,7 +51,7 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( logic LeftShiftQm; // should the divsqrt result be shifted one to the left logic RightShift; // shift right by 1 - // *** 4/16/24 this code is a mess and needs cleaning and explaining + // dh 4/16/24 this code is a mess and needs cleaning and explaining // define bit widths // seems to shift by 0, 1, or 2. right and left shift is confusing @@ -61,20 +61,20 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) ( // - a one has to propagate all the way through a sum. so we can leave the bottom statement alone assign LZAPlus1 = Shifted[P.NORMSHIFTSZ-1]; - // correct the shifting of the divsqrt caused by producing a result in (0.5, 2) range // condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm) - assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); - - assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm; + assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1)); - // one bit right shift for FMA or division - mux2 #(P.NORMSHIFTSZ) corrmux({Shifted[P.NORMSHIFTSZ-3:0], 2'b00}, {Shifted[P.NORMSHIFTSZ-2:1], 2'b00}, RightShift, CorrShifted); - + // Determine the shif for either FMA or divsqrt + assign RightShift = FmaOp ? LZAPlus1 : LeftShiftQm; + + // possible one bit right shift for FMA or division // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits always_comb - if (FmaOp | (DivOp & ~DivResSubnorm)) Mf = CorrShifted; - else Mf = Shifted[P.NORMSHIFTSZ-1:0]; + if (FmaOp | (DivOp & ~DivResSubnorm)) // one bit shift for FMA or divsqrt + if (RightShift) Mf = {Shifted[P.NORMSHIFTSZ-2:1], 2'b00}; + else Mf = {Shifted[P.NORMSHIFTSZ-3:0], 2'b00}; + else Mf = Shifted[P.NORMSHIFTSZ-1:0]; // convert and subnormal division result // Determine sum's exponent // main exponent issues: diff --git a/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv index b9dbf4b9e..bb655942d 100644 --- a/src/fpu/postproc/specialcase.sv +++ b/src/fpu/postproc/specialcase.sv @@ -6,7 +6,7 @@ // // Purpose: special case selection // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 2e87d17fc..b24554fc0 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -6,7 +6,7 @@ // // Purpose: unpack X, Y, Z floating-point inputs // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index a6c421e5c..1b27c439b 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -6,7 +6,7 @@ // // Purpose: unpack input: extract sign, exponent, significand, characteristics // -// Documentation: RISC-V System on Chip Design Chapter 13 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index dc5f6450c..91e01c7ab 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -34,7 +34,7 @@ module aplusbeq0 #(parameter WIDTH = 8) ( logic [WIDTH-1:0] orshift; // The sum is zero if the bitwise XOR is equal to the bitwise OR shifted left by 1, for all columns - // *** explain, cite book + // See J. A. Prabhu and G. Zyner, "167 MHz radix-8 divide and square root using overlapped radix-2 stages," IEEE Symp. Computer Arithmetic, 1995, pp. 155-162. assign x = a ^ b; assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0}; diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 78b816c3c..8af273fc5 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -29,8 +29,5 @@ module decoder #(parameter BINARY_BITS = 3) ( output logic [(2**BINARY_BITS)-1:0] onehot ); - // *** Double check whether this synthesizes as expected - // -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists assign onehot = 1 << binary; - endmodule diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index a0dd5aef4..2c15716d9 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -44,11 +44,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE output logic [WIDTH-1:0] dout ); - bit [WIDTH-1:0] RAM[DEPTH-1:0]; - - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// // TRUE SRAM macro - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; // 64 x 128-bit SRAM @@ -79,10 +77,11 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// // READ first SRAM model - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// end else begin: ram + bit [WIDTH-1:0] RAM[DEPTH-1:0]; integer i; if (PRELOAD_ENABLED) begin diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv index a030d2aab..fb41d99bf 100644 --- a/src/generic/mem/ram1p1rwe.sv +++ b/src/generic/mem/ram1p1rwe.sv @@ -41,11 +41,9 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( output logic [WIDTH-1:0] dout ); - bit [WIDTH-1:0] RAM[DEPTH-1:0]; - - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// // TRUE SRAM macro - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray // 64 x 128-bit SRAM ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), @@ -64,12 +62,15 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) ( .A(addr), .D(din), .BWEB('0), .Q(dout)); - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// // READ first SRAM model - // *************************************************************************** + ////////////////////////////////////////////////////////////////////////////// end else begin: ram - // *** Vivado is not implementing this as block ram for some reason. + // Vivado is not implementing this as block ram for some reason. // The version with byte write enables it correctly infers block ram. + + bit [WIDTH-1:0] RAM[DEPTH-1:0]; + integer i; // Combinational read: register address and read after clock edge diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index c4cee8b7e..5a677ffaa 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -44,13 +44,12 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) output logic [WIDTH-1:0] rd1 ); - bit [WIDTH-1:0] mem[DEPTH-1:0]; localparam SRAMWIDTH = 32; localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; - // *************************************************************************** - // TRUE Smem macro - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// + // TRUE SRAM macro + /////////////////////////////////////////////////////////////////////////////// if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin @@ -105,24 +104,26 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) .QA(SRAMReadData), .QB()); - end else begin + end else begin:ram - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// // READ first SRAM model - // *************************************************************************** + /////////////////////////////////////////////////////////////////////////////// + + bit [WIDTH-1:0] RAM[DEPTH-1:0]; integer i; /* initial begin // initialize memory for simulation only; not needed because done in the testbench now integer j; for (j=0; j < DEPTH; j++) - mem[j] = '0; + RAM[j] = '0; end */ // Read logic [$clog2(DEPTH)-1:0] ra1d; flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); - assign rd1 = mem[ra1d]; + assign rd1 = RAM[ra1d]; // Write divided into part for bytes and part for extra msbs // coverage off @@ -131,13 +132,13 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) always @(posedge clk) if (ce2 & we2) for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= wd2[i*8 +: 8]; + if(bwe2[i]) RAM[wa2][i*8 +: 8] <= wd2[i*8 +: 8]; // coverage on if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8]; + RAM[wa2][WIDTH-1:WIDTH-WIDTH%8] <= wd2[WIDTH-1:WIDTH-WIDTH%8]; end endmodule diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 5d2611dda..a5b6e319d 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -6,7 +6,7 @@ // // Purpose: Determine stalls and flushes // -// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 74eb6f7f6..e142de1e7 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 76734f97f..1b05b43e0 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 083033d53..5fc4e8b49 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -7,7 +7,7 @@ // // Purpose: Bit reverse submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 97a0caa45..834270685 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -7,7 +7,7 @@ // // Purpose: Top level bit manipulation instruction decoder // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/byteop.sv b/src/ieu/bmu/byteop.sv index 263680aea..33a0dc332 100644 --- a/src/ieu/bmu/byteop.sv +++ b/src/ieu/bmu/byteop.sv @@ -7,7 +7,7 @@ // // Purpose: RISCV bitmanip byte-wise operation unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index f32fcece9..2ea45606f 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -7,7 +7,7 @@ // // Purpose: Carry-Less multiplication unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index dff468257..f0bc5f72d 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -7,7 +7,7 @@ // // Purpose: Count Instruction Submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 66d69fb21..268f9dad5 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -7,7 +7,7 @@ // // Purpose: Sign/Zero Extension Submodule // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 838468fa1..435c8dff1 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -5,7 +5,7 @@ // // Purpose: Population Count // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index f9957c787..d5f9b269c 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBB top level unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index cb63eb85a..e11e94167 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBC top-level unit // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/comparator.sv b/src/ieu/comparator.sv index 466167fb3..175e7df08 100644 --- a/src/ieu/comparator.sv +++ b/src/ieu/comparator.sv @@ -7,7 +7,7 @@ // // Purpose: Branch comparison // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index f8d3e2122..21f024942 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -7,7 +7,7 @@ // // Purpose: Top level controller module // -// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 30848ea6d..50a61fc2a 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -7,7 +7,7 @@ // // Purpose: Wally Integer Datapath // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 11ab14419..437797859 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -7,7 +7,7 @@ // // Purpose: Produce sign-extended immediates from various formats // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 38d50e3c3..362ca132b 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -6,7 +6,7 @@ // // Purpose: Integer Execution Unit: datapath and controller // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index 0cb6beaaa..48359d3ca 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -7,7 +7,7 @@ // // Purpose: 3-port register file // -// Documentation: RISC-V System on Chip Design Chapter 4 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 52d87bb1d..8d4da28d9 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V 32/64 bit shifter // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 5129e9043..85eda07ca 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -7,7 +7,7 @@ // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // -// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index e9e0b5bfd..1ac95bed9 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -8,7 +8,7 @@ // Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions. // It also guesses the type of instrution; jalr(r), return, jump (jr), or branch. // -// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 5a8c65ecf..512dacfd5 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -6,10 +6,6 @@ // Modified: 18 January 2023 // // Purpose: Expand 16-bit compressed instructions to 32 bits -// -// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1) -// RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97 -// *** probably need more documentation in this file since the book is very light on decompression. // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 49e4ddc82..5b82aac76 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -9,7 +9,7 @@ // cache line boundaries or if instruction address without a cache crosses // XLEN/8 boundary. // -// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/align.sv b/src/lsu/align.sv index c28c1b9cf..25a2c99d7 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -9,7 +9,7 @@ // It is simlar to the IFU's spill module and probably could be merged together with // some effort. // -// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index a6ee53e73..bc8a29471 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -7,7 +7,7 @@ // // Purpose: Performs AMO operations // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -73,7 +73,7 @@ module amoalu import cvw::*; #(parameter cvw_t P) ( 5'b10100: y = cmp ? a : b; // amomax 5'b11000: y = cmp ? a : b; // amominu 5'b11100: y = cmp ? a : b; // amomaxu - default: y = 'x; // undefined; *** could change to b for efficiency + default: y = 'x; // undefined endcase // sign extend output if necessary for w64 diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 704eb4c62..e318260ab 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -7,7 +7,7 @@ // // Purpose: Wrapper for amoalu and lrsc // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 1386db96f..5bd46deb9 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -7,7 +7,7 @@ // // Purpose: tightly integrated memory into the LSU. // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/endianswap.sv b/src/lsu/endianswap.sv index 7c042886a..3634e2322 100644 --- a/src/lsu/endianswap.sv +++ b/src/lsu/endianswap.sv @@ -7,7 +7,7 @@ // // Purpose: Swap byte order for Big-Endian accesses // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv index 5981035c1..437907e55 100644 --- a/src/lsu/lrsc.sv +++ b/src/lsu/lrsc.sv @@ -8,7 +8,7 @@ // Purpose: Load Reserved / Store Conditional unit // Track the reservation and squash the store if it fails // -// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 43176e04b..f0d046679 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -9,7 +9,7 @@ // HPTW, DMMU, data cache, interface to external bus // Atomic, Endian swap, and subword read/write logic // -// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv index a0e1bfc2f..40e3c11c6 100644 --- a/src/lsu/subwordread.sv +++ b/src/lsu/subwordread.sv @@ -7,7 +7,7 @@ // // Purpose: Extract subwords and sign extend for reads // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv index eec6fe020..4ae097cc3 100644 --- a/src/lsu/subwordwrite.sv +++ b/src/lsu/subwordwrite.sv @@ -7,7 +7,7 @@ // // Purpose: Masking and muxing for subword writes // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index fc1f95c4e..cbe4070cc 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -7,7 +7,7 @@ // // Purpose: On-chip RAM, external to core // -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/div.sv b/src/mdu/div.sv index 2ae35d8f4..66fe5d9d4 100644 --- a/src/mdu/div.sv +++ b/src/mdu/div.sv @@ -6,7 +6,7 @@ // // Purpose: Restoring integer division using a shift register and subtractor // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/divstep.sv b/src/mdu/divstep.sv index f478ad86f..d47742fa9 100644 --- a/src/mdu/divstep.sv +++ b/src/mdu/divstep.sv @@ -6,7 +6,7 @@ // // Purpose: Radix-2 restoring integer division step. k steps are used in div // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 8918e5830..34646ac94 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -6,7 +6,7 @@ // // Purpose: M extension multiply and divide // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mdu/mul.sv b/src/mdu/mul.sv index 65eaefd82..7c3f13a85 100644 --- a/src/mdu/mul.sv +++ b/src/mdu/mul.sv @@ -6,7 +6,7 @@ // // Purpose: Integer multiplication // -// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv index bf092dbc6..f4de5a7b7 100644 --- a/src/mmu/adrdec.sv +++ b/src/mmu/adrdec.sv @@ -6,7 +6,7 @@ // // Purpose: Address decoder // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv index d71fef82a..2ef7c25f1 100644 --- a/src/mmu/adrdecs.sv +++ b/src/mmu/adrdecs.sv @@ -6,7 +6,7 @@ // // Purpose: All the address decoders for peripherals // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 32eef1bf6..b86ee6a95 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -10,7 +10,7 @@ // // Purpose: Hardware Page Table Walker // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -281,7 +281,6 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back // to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but // rather than physical address of the translated instruction/data. So we must generate the exception. - // *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546) flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index ec41773a8..c9d4c3415 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -6,7 +6,7 @@ // // Purpose: Memory management unit, including TLB, PMA, PMP // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -95,7 +95,7 @@ module mmu import cvw::*; #(parameter cvw_t P, end else begin:tlb // just pass address through as physical assign Translate = 1'b0; assign TLBMiss = 1'b0; - assign TLBHit = 1'b1; // *** is this necessary + assign TLBHit = 1'b0; assign TLBPageFault = 1'b0; assign PBMemoryType = 2'b00; end diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index b1953cb9b..f2a2e984b 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -8,7 +8,7 @@ // the memory region accessed. // Can report illegal accesses to the trap unit and cause a fault. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 9f5245081..71a6b890a 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -10,7 +10,7 @@ // naturally aligned power-of-two region/NAPOT), then selects the // output based on which mode is input. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 30a525744..a97b7ff2e 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -9,7 +9,7 @@ // Can raise an access fault on illegal reads, writes, and instruction // fetches. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv index 5fbd10caf..b1d0966cf 100644 --- a/src/mmu/tlb/tlb.sv +++ b/src/mmu/tlb/tlb.sv @@ -9,7 +9,7 @@ // Purpose: Translation lookaside buffer // Cache of virtural-to-physical address translations // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index aa569f2dd..06b66efcc 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -9,7 +9,7 @@ // Purpose: Stores virtual page numbers with cached translations. // Determines whether a given virtual page number is in the TLB. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index f5856ef56..057c8766b 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -9,7 +9,7 @@ // Purpose: CAM line for the translation lookaside buffer (TLB) // Determines whether a virtual page number matches the stored key. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv index 83074deb3..a75208a14 100644 --- a/src/mmu/tlb/tlbcontrol.sv +++ b/src/mmu/tlb/tlbcontrol.sv @@ -6,7 +6,7 @@ // // Purpose: Control signals for TLB // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 4776b5afb..96359590b 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -7,7 +7,7 @@ // Purpose: Implementation of bit pseudo least-recently-used algorithm for // cache evictions. Outputs the index of the next entry to be written. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv index d615d1370..502d3ef83 100644 --- a/src/mmu/tlb/tlbmixer.sv +++ b/src/mmu/tlb/tlbmixer.sv @@ -9,7 +9,7 @@ // number with segments from the second, based on the page type. // NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 620f338a1..3b329705d 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -8,7 +8,7 @@ // Outputs the physical page number and access bits of the current // virtual address on a TLB hit. // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv index 910db3aec..0b3e3994a 100644 --- a/src/mmu/tlb/tlbramline.sv +++ b/src/mmu/tlb/tlbramline.sv @@ -6,7 +6,7 @@ // // Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/mmu/tlb/vm64check.sv b/src/mmu/tlb/vm64check.sv index d8168dac2..229bb5a5f 100644 --- a/src/mmu/tlb/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -6,7 +6,7 @@ // // Purpose: Check for good upper address bits in RV64 mode // -// Documentation: RISC-V System on Chip Design Chapter 8 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index fac432251..a9d38028e 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -8,7 +8,7 @@ // Purpose: Counter Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index f0704d0cf..fd078b04b 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -7,7 +7,7 @@ // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index fafc5c845..b3db38e8a 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -7,7 +7,7 @@ // Purpose: Interrupt Control & Status Registers (IP, EI) // See RISC-V Privileged Mode Specification 20190608 & 20210108 draft // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 348002e46..7aaf4c052 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -11,7 +11,7 @@ // - Disabling portions of the instruction set with bits of the MISA register // - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 9623aa8b5..ebd468ad6 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -8,7 +8,7 @@ // Purpose: Supervisor-Mode Control and Status Registers // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 161bf521c..22f34124c 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -7,7 +7,7 @@ // Purpose: Status register (and environment configuration register and others shared across modes) // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -66,7 +66,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0, STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE, /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0}; - assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value. Spec is not clear what it should be. + assign MSTATUSH_REGW = '0; // does not exist when XLEN=64, and accessing will throw an illegal instruction end else begin: csrsr32 // RV32 assign MSTATUS_REGW = {STATUS_SD, 8'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index 62ac86c8d..eeb364a89 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -6,7 +6,7 @@ // // Purpose: User-Mode Control and Status Registers for Floating Point // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 60828a3f2..6321413d4 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -7,7 +7,7 @@ // Purpose: Decode Privileged & related instructions // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index c0dffcaa6..a02d59383 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -7,7 +7,7 @@ // Purpose: Implements the CSRs, Exceptions, and Privileged operations // See RISC-V Privileged Mode Specification 20190608 // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privmode.sv b/src/privileged/privmode.sv index f1c5bfd76..f9a38d501 100644 --- a/src/privileged/privmode.sv +++ b/src/privileged/privmode.sv @@ -6,7 +6,7 @@ // // Purpose: Track privilege mode. Change on traps and returns. // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv index ed43571bd..4cab65c34 100644 --- a/src/privileged/privpiperegs.sv +++ b/src/privileged/privpiperegs.sv @@ -6,7 +6,7 @@ // // Purpose: Pipeline registers for early exceptions // -// Documentation: RISC-V System on Chip Design Chapter 5 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index 788b39618..247bfe678 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -6,7 +6,7 @@ // // Purpose: Handle Traps: Exceptions and Interrupts // -// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9) +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index df41c9541..84979ddee 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -5,7 +5,7 @@ // // Purpose: AHB to APB bridge // -// Documentation: RISC-V System on Chip Design Chapter 6 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index c416f2938..58f80c26e 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -7,7 +7,7 @@ // Purpose: Core-Local Interruptor // See FE310-G002-Manual-v19p05 for specifications // -// Documentation: RISC-V System on Chip Design Chapter 15 +// Documentation: RISC-V System on Chip Design // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -85,7 +85,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( if (entry == CLINT_MTIMECMP) begin for(i=0;i> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k]; /* verilator lint_off WIDTHTRUNC */ - // *** lint error: address trunc warning for shadowram index + // avoid lint error: address trunc warning for shadowram index ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; /* verilator lint_on WIDTHTRUNC */ end diff --git a/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv index 429ff8489..f4ec8523d 100644 --- a/testbench/common/instrTrackerTB.sv +++ b/testbench/common/instrTrackerTB.sv @@ -34,5 +34,5 @@ module instrTrackerTB( instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB edec(InstrE, InstrEName); instrNameDecTB mdec(InstrM, InstrMName); - instrNameDecTB wdec(InstrW, InstrWName); // *** delete this because InstrW is deleted from IFU + instrNameDecTB wdec(InstrW, InstrWName); endmodule diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index b8a6389cb..967cf672b 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -261,11 +261,11 @@ module loggers import cvw::*; #(parameter cvw_t P, $fwrite(file, "BEGIN %s\n", memfilename); $fwrite(CFIfile, "BEGIN %s\n", memfilename); end - if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if(dut.core.ifu.IClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin direction = PCSrcM ? "t" : "n"; $fwrite(file, "%h %s\n", dut.core.PCM, direction); end - if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin + if((|dut.core.ifu.IClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin direction = PCSrcM ? "t" : "n"; $fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction); end diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 17def063c..eed068f54 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -496,13 +496,21 @@ module testbench; if (LoadMem) begin if (TEST == "buildroot") begin memFile = $fopen(bootmemfilename, "rb"); + if (memFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile); $fclose(memFile); memFile = $fopen(memfilename, "rb"); - readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.RAM, memFile); + if (memFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end + readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile); $fclose(memFile); end else - $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.RAM); + $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -511,7 +519,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncoregen.uncore.ram.ram.memory.ram.RAM[ShadowIndex - BaseIndex]; end end end @@ -519,7 +527,7 @@ module testbench; if (P.DTIM_SUPPORTED) begin always @(posedge clk) begin if (LoadMem) begin - $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.ram.RAM); $display("Read memfile %s", memfilename); end if (CopyRAM) begin @@ -528,7 +536,7 @@ module testbench; EndIndex = (end_signature_addr >> LogXLEN) + 8; BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN; for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin - testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.RAM[ShadowIndex - BaseIndex]; + testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.core.lsu.dtim.dtim.ram.ram.RAM[ShadowIndex - BaseIndex]; end end end @@ -539,7 +547,7 @@ module testbench; always @(posedge clk) if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) - dut.uncoregen.uncore.ram.ram.memory.RAM[adrindex] = '0; + dut.uncoregen.uncore.ram.ram.memory.ram.RAM[adrindex] = '0; //////////////////////////////////////////////////////////////////////////////// // Actual hardware @@ -725,7 +733,7 @@ end $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); $fatal; end - end else begin // for buildroot use the binary instead to load teh reference model. + end else begin // for buildroot use the binary instead to load the reference model. if (!rvviRefInit("")) begin // still have to call with nothing $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); $fatal; @@ -955,7 +963,7 @@ task automatic updateProgramAddrLabelArray; returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr); if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex(); end - end + end // if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile); // if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);