From 54b8e7c62930bca16ed2fd24c876a408e63d07eb Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 26 Feb 2023 09:58:34 -0800
Subject: [PATCH] Access faults are geted by ~TLBMiss rather than ~(Translate &
 ~TLBHit)

---
 src/mmu/mmu.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index 5b5248161..0193a5478 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -120,9 +120,9 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
 
   // Access faults
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
-  assign InstrAccessFaultF    = (PMAInstrAccessFaultF    | PMPInstrAccessFaultF)    & ~(Translate & ~TLBHit);
-  assign LoadAccessFaultM     = (PMALoadAccessFaultM     | PMPLoadAccessFaultM)     & ~(Translate & ~TLBHit);
-  assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
+  assign InstrAccessFaultF    = (PMAInstrAccessFaultF    | PMPInstrAccessFaultF)    & ~TLBMiss;
+  assign LoadAccessFaultM     = (PMALoadAccessFaultM     | PMPLoadAccessFaultM)     & ~TLBMiss;
+  assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~TLBMiss;
 
   // Misaligned faults
    always_comb