Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas

pipelined/regression/Makefile

@@ -5,7 +5,7 @@ make allclean:
 make clean:
 	make clean -C ../../addins/riscv-arch-test
 	make clean -C ../../tests/wally-riscv-arch-test
-	make allclean -C ../../tests/imperas-riscv-tests
+#	make allclean -C ../../tests/imperas-riscv-tests
 
 make all:
 	# *** Build old tests/imperas-riscv-tests for now;

pipelined/regression/makefile-memfile

@@ -2,8 +2,10 @@ ROOT	:= ../..
 SUFFIX	:= work
 ARCHDIR	:= $(ROOT)/addins/riscv-arch-test
 WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
+# IMPERASDIR	:= $(ROOT)/tests/imperas-riscv-tests
+# ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX)
 IMPERASDIR	:= $(ROOT)/tests/imperas-riscv-tests
-ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX)
+ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) 
 
 ELFFILES	?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf")
 MEMFILES ?= $(ELFFILES:.elf=.elf.memfile)

pipelined/src/fma/fma.do

@@ -8,7 +8,7 @@ onbreak {resume}
 # create library
 vlib worklib
 
-vlog -lint -work worklib fma16.sv testbench.sv
+vlog -lint -work worklib fma16.sv testbench.v
 vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
 vsim -lib worklib testbenchopt