From 53de2bf78278e0572234f3b6d4dfbf5483c45c8a Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 18 Apr 2023 15:23:22 -0500 Subject: [PATCH] AHB triggers write, but AXI side doesn't update. --- fpga/constraints/debug2.xdc | 135 ++++++++++++++++++++++++++- fpga/generator/xlnx_axi_crossbar.tcl | 4 +- fpga/src/fpgaTop.v | 66 ++++++------- 3 files changed, 168 insertions(+), 37 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 13733e579..ec1d1d550 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -748,9 +748,9 @@ connect_debug_port u_ila_0/probe143 [get_nets [list {m_axi_awcache[0]} {m_axi_aw create_debug_port u_ila_0 probe -set_property port_width 31 [get_debug_ports u_ila_0/probe144] +set_property port_width 32 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} ]] +connect_debug_port u_ila_0/probe144 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]}]] create_debug_port u_ila_0 probe @@ -1016,3 +1016,134 @@ create_debug_port u_ila_0 probe set_property port_width 8 [get_debug_ports u_ila_0/probe191] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe191] connect_debug_port u_ila_0/probe191 [get_nets [list {axiSDC/clock_divider_reg[0]} {axiSDC/clock_divider_reg[1]} {axiSDC/clock_divider_reg[2]} {axiSDC/clock_divider_reg[3]} {axiSDC/clock_divider_reg[4]} {axiSDC/clock_divider_reg[5]} {axiSDC/clock_divider_reg[6]} {axiSDC/clock_divider_reg[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe192] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe192] +connect_debug_port u_ila_0/probe192 [get_nets [list {SDCin_axi_awaddr[0]} {SDCin_axi_awaddr[1]} {SDCin_axi_awaddr[2]} {SDCin_axi_awaddr[3]} {SDCin_axi_awaddr[4]} {SDCin_axi_awaddr[5]} {SDCin_axi_awaddr[6]} {SDCin_axi_awaddr[7]} {SDCin_axi_awaddr[8]} {SDCin_axi_awaddr[9]} {SDCin_axi_awaddr[10]} {SDCin_axi_awaddr[11]} {SDCin_axi_awaddr[12]} {SDCin_axi_awaddr[13]} {SDCin_axi_awaddr[14]} {SDCin_axi_awaddr[15]} {SDCin_axi_awaddr[16]} {SDCin_axi_awaddr[17]} {SDCin_axi_awaddr[18]} {SDCin_axi_awaddr[19]} {SDCin_axi_awaddr[20]} {SDCin_axi_awaddr[21]} {SDCin_axi_awaddr[22]} {SDCin_axi_awaddr[23]} {SDCin_axi_awaddr[24]} {SDCin_axi_awaddr[25]} {SDCin_axi_awaddr[26]} {SDCin_axi_awaddr[27]} {SDCin_axi_awaddr[28]} {SDCin_axi_awaddr[29]} {SDCin_axi_awaddr[30]} {SDCin_axi_awaddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe193] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe193] +connect_debug_port u_ila_0/probe193 [get_nets [list {SDCin_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe194] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe194] +connect_debug_port u_ila_0/probe194 [get_nets [list {SDCin_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe195] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe195] +connect_debug_port u_ila_0/probe195 [get_nets [list {SDCin_axi_wdata[0]} {SDCin_axi_wdata[1]} {SDCin_axi_wdata[2]} {SDCin_axi_wdata[3]} {SDCin_axi_wdata[4]} {SDCin_axi_wdata[5]} {SDCin_axi_wdata[6]} {SDCin_axi_wdata[7]} {SDCin_axi_wdata[8]} {SDCin_axi_wdata[9]} {SDCin_axi_wdata[10]} {SDCin_axi_wdata[11]} {SDCin_axi_wdata[12]} {SDCin_axi_wdata[13]} {SDCin_axi_wdata[14]} {SDCin_axi_wdata[15]} {SDCin_axi_wdata[16]} {SDCin_axi_wdata[17]} {SDCin_axi_wdata[18]} {SDCin_axi_wdata[19]} {SDCin_axi_wdata[20]} {SDCin_axi_wdata[21]} {SDCin_axi_wdata[22]} {SDCin_axi_wdata[23]} {SDCin_axi_wdata[24]} {SDCin_axi_wdata[25]} {SDCin_axi_wdata[26]} {SDCin_axi_wdata[27]} {SDCin_axi_wdata[28]} {SDCin_axi_wdata[29]} {SDCin_axi_wdata[30]} {SDCin_axi_wdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe196] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe196] +connect_debug_port u_ila_0/probe196 [get_nets [list {SDCin_axi_wvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe197] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe197] +connect_debug_port u_ila_0/probe197 [get_nets [list {SDCin_axi_wready}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe198] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe198] +connect_debug_port u_ila_0/probe198 [get_nets [list {SDCin_axi_bresp[0]} {SDCin_axi_bresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe199] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe199] +connect_debug_port u_ila_0/probe199 [get_nets [list {SDCin_axi_bvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe200] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe200] +connect_debug_port u_ila_0/probe200 [get_nets [list {SDCin_axi_bready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe201] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe201] +connect_debug_port u_ila_0/probe201 [get_nets [list {SDCin_axi_araddr[0]} {SDCin_axi_araddr[1]} {SDCin_axi_araddr[2]} {SDCin_axi_araddr[3]} {SDCin_axi_araddr[4]} {SDCin_axi_araddr[5]} {SDCin_axi_araddr[6]} {SDCin_axi_araddr[7]} {SDCin_axi_araddr[8]} {SDCin_axi_araddr[9]} {SDCin_axi_araddr[10]} {SDCin_axi_araddr[11]} {SDCin_axi_araddr[12]} {SDCin_axi_araddr[13]} {SDCin_axi_araddr[14]} {SDCin_axi_araddr[15]} {SDCin_axi_araddr[16]} {SDCin_axi_araddr[17]} {SDCin_axi_araddr[18]} {SDCin_axi_araddr[19]} {SDCin_axi_araddr[20]} {SDCin_axi_araddr[21]} {SDCin_axi_araddr[22]} {SDCin_axi_araddr[23]} {SDCin_axi_araddr[24]} {SDCin_axi_araddr[25]} {SDCin_axi_araddr[26]} {SDCin_axi_araddr[27]} {SDCin_axi_araddr[28]} {SDCin_axi_araddr[29]} {SDCin_axi_araddr[30]} {SDCin_axi_araddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe202] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe202] +connect_debug_port u_ila_0/probe202 [get_nets [list {SDCin_axi_arvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe203] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe203] +connect_debug_port u_ila_0/probe203 [get_nets [list {SDCin_axi_arready}]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe204] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe204] +connect_debug_port u_ila_0/probe204 [get_nets [list {SDCin_axi_rdata[0]} {SDCin_axi_rdata[1]} {SDCin_axi_rdata[2]} {SDCin_axi_rdata[3]} {SDCin_axi_rdata[4]} {SDCin_axi_rdata[5]} {SDCin_axi_rdata[6]} {SDCin_axi_rdata[7]} {SDCin_axi_rdata[8]} {SDCin_axi_rdata[9]} {SDCin_axi_rdata[10]} {SDCin_axi_rdata[11]} {SDCin_axi_rdata[12]} {SDCin_axi_rdata[13]} {SDCin_axi_rdata[14]} {SDCin_axi_rdata[15]} {SDCin_axi_rdata[16]} {SDCin_axi_rdata[17]} {SDCin_axi_rdata[18]} {SDCin_axi_rdata[19]} {SDCin_axi_rdata[20]} {SDCin_axi_rdata[21]} {SDCin_axi_rdata[22]} {SDCin_axi_rdata[23]} {SDCin_axi_rdata[24]} {SDCin_axi_rdata[25]} {SDCin_axi_rdata[26]} {SDCin_axi_rdata[27]} {SDCin_axi_rdata[28]} {SDCin_axi_rdata[29]} {SDCin_axi_rdata[30]} {SDCin_axi_rdata[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe205] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe205] +connect_debug_port u_ila_0/probe205 [get_nets [list {SDCin_axi_rresp[0]} {SDCin_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe206] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe206] +connect_debug_port u_ila_0/probe206 [get_nets [list {SDCin_axi_rvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe207] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe207] +connect_debug_port u_ila_0/probe207 [get_nets [list {SDCin_axi_rready}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe208] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe208] +connect_debug_port u_ila_0/probe208 [get_nets [list {s01_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe209] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe209] +connect_debug_port u_ila_0/probe209 [get_nets [list {s01_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe210] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe210] +connect_debug_port u_ila_0/probe210 [get_nets [list {s00_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe211] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe211] +connect_debug_port u_ila_0/probe211 [get_nets [list {s00_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe212] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe212] +connect_debug_port u_ila_0/probe212 [get_nets [list {axi4in_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe213] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe213] +connect_debug_port u_ila_0/probe213 [get_nets [list {axi4in_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe214] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe214] +connect_debug_port u_ila_0/probe214 [get_nets [list {SDCout_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe215] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe215] +connect_debug_port u_ila_0/probe215 [get_nets [list {SDCout_axi_awready}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe216] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe216] +connect_debug_port u_ila_0/probe216 [get_nets [list {m01_axi_awvalid}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe217] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe217] +connect_debug_port u_ila_0/probe217 [get_nets [list {m01_axi_awready}]] diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl index 1d9eb4e78..ed44d9997 100644 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -19,8 +19,8 @@ create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module set_property -dict [list CONFIG.NUM_SI {2} \ CONFIG.DATA_WIDTH {64} \ CONFIG.ID_WIDTH {4} \ - CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + # CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + # CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 03758249e..42957f63b 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -199,8 +199,8 @@ module fpgaTop wire [2:0]s00_axi_awprot; wire [3:0]s00_axi_awregion; wire [3:0]s00_axi_awqos; - wire s00_axi_awvalid; - wire s00_axi_awready; + (* mark_debug = "true" *) wire s00_axi_awvalid; + (* mark_debug = "true" *) wire s00_axi_awready; wire [63:0]s00_axi_wdata; wire [7:0]s00_axi_wstrb; wire s00_axi_wlast; @@ -242,8 +242,8 @@ module fpgaTop wire [2:0]s01_axi_awprot; wire [3:0]s01_axi_awregion; wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - wire s01_axi_awvalid; - wire s01_axi_awready; + (* mark_debug = "true" *) wire s01_axi_awvalid; + (* mark_debug = "true" *) wire s01_axi_awready; wire [63:0]s01_axi_wdata; wire [7:0]s01_axi_wstrb; wire s01_axi_wlast; @@ -279,8 +279,8 @@ module fpgaTop wire [2:0]axi4in_axi_awprot; wire [3:0]axi4in_axi_awregion; wire [3:0]axi4in_axi_awqos; - wire axi4in_axi_awvalid; - wire axi4in_axi_awready; + (* mark_debug = "true" *) wire axi4in_axi_awvalid; + (* mark_debug = "true" *) wire axi4in_axi_awready; wire [31:0]axi4in_axi_wdata; wire [3:0]axi4in_axi_wstrb; wire axi4in_axi_wlast; @@ -307,25 +307,25 @@ module fpgaTop wire axi4in_axi_rready; // AXI4 to AXI4-Lite Protocol converter output - wire [31:0]SDCin_axi_awaddr; - wire [2:0]SDCin_axi_awprot; - wire SDCin_axi_awvalid; - wire SDCin_axi_awready; - wire [31:0]SDCin_axi_wdata; - wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wvalid; - wire SDCin_axi_wready; - wire [1:0]SDCin_axi_bresp; - wire SDCin_axi_bvalid; - wire SDCin_axi_bready; - wire [31:0]SDCin_axi_araddr; - wire [2:0]SDCin_axi_arprot; - wire SDCin_axi_arvalid; - wire SDCin_axi_arready; - wire [31:0]SDCin_axi_rdata; - wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rvalid; - wire SDCin_axi_rready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; + (* mark_debug = "true" *) wire SDCin_axi_awvalid; + (* mark_debug = "true" *) wire SDCin_axi_awready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; + (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; + (* mark_debug = "true" *) wire SDCin_axi_wvalid; + (* mark_debug = "true" *) wire SDCin_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; + (* mark_debug = "true" *) wire SDCin_axi_bvalid; + (* mark_debug = "true" *) wire SDCin_axi_bready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; + (* mark_debug = "true" *) wire SDCin_axi_arvalid; + (* mark_debug = "true" *) wire SDCin_axi_arready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; + (* mark_debug = "true" *) wire SDCin_axi_rvalid; + (* mark_debug = "true" *) wire SDCin_axi_rready; // ---------------------------------------------------------------- // 32to64 dwidth converter input interface ----------------------- @@ -338,8 +338,8 @@ module fpgaTop wire [2:0]SDCout_axi_awprot; wire [3:0]SDCout_axi_awregion; wire [3:0]SDCout_axi_awqos; - wire SDCout_axi_awvalid; - wire SDCout_axi_awready; + (* mark_debug = "true" *) wire SDCout_axi_awvalid; + (* mark_debug = "true" *) wire SDCout_axi_awready; wire [31:0]SDCout_axi_wdata; wire [3:0]SDCout_axi_wstrb; wire SDCout_axi_wlast; @@ -376,8 +376,8 @@ module fpgaTop wire [2:0]m01_axi_awprot; wire [3:0]m01_axi_awregion; wire [3:0]m01_axi_awqos; - wire m01_axi_awvalid; - wire m01_axi_awready; + (* mark_debug = "true" *) wire m01_axi_awvalid; + (* mark_debug = "true" *) wire m01_axi_awready; wire [63:0]m01_axi_wdata; wire [3:0]m01_axi_wstrb; wire m01_axi_wlast; @@ -571,7 +571,7 @@ module fpgaTop .aresetn(peripheral_aresetn), // Connect Masters - .s_axi_awid({4'b0001, m_axi_awid}), + .s_axi_awid({4'b1000, m_axi_awid}), .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), @@ -591,7 +591,7 @@ module fpgaTop .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b0001, m_axi_arid}), + .s_axi_arid({4'b1000, m_axi_arid}), .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), @@ -627,7 +627,7 @@ module fpgaTop .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b0001, s00_axi_bid}), + .m_axi_bid({4'b1000, s00_axi_bid}), .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), .m_axi_bready({s01_axi_bready, s00_axi_bready}), @@ -643,7 +643,7 @@ module fpgaTop .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b0, s00_axi_rid}), + .m_axi_rid({4'b1000, s00_axi_rid}), .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}),