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https://github.com/openhwgroup/cvw
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csr cleanup
This commit is contained in:
parent
b7f579a146
commit
53d0d28828
@ -201,6 +201,7 @@ module csr #(parameter
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.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
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.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
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.MExtInt, .SExtInt, .MTimerInt, .MSwInt,
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.MExtInt, .SExtInt, .MTimerInt, .MSwInt,
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.MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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.MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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csrsr csrsr(.clk, .reset, .StallW,
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csrsr csrsr(.clk, .reset, .StallW,
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.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
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.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
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.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
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.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
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@ -209,6 +210,7 @@ module csr #(parameter
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
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.STATUS_FS, .BigEndianM);
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.STATUS_FS, .BigEndianM);
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
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csrm csrm(.clk, .reset, .InstrValidNotFlushedM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
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@ -217,6 +219,9 @@ module csr #(parameter
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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if (`S_SUPPORTED) begin:csrs
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csrs csrs(.clk, .reset, .InstrValidNotFlushedM,
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csrs csrs(.clk, .reset, .InstrValidNotFlushedM,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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@ -225,10 +230,28 @@ module csr #(parameter
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.SCOUNTEREN_REGW,
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.SCOUNTEREN_REGW,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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end else begin
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assign WriteSSTATUSM = 0;
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assign CSRSReadValM = 0;
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assign SEPC_REGW = 0;
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assign STVEC_REGW = 0;
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assign SCOUNTEREN_REGW = 0;
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assign SATP_REGW = 0;
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assign IllegalCSRSAccessM = 1;
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end
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// Floating Point CSRs in User Mode only needed if Floating Point is supported
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if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
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csru csru(.clk, .reset, .InstrValidNotFlushedM,
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csru csru(.clk, .reset, .InstrValidNotFlushedM,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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.IllegalCSRUAccessM);
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end else begin
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assign FRM_REGW = 0;
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assign CSRUReadValM = 0;
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assign IllegalCSRUAccessM = 1;
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end
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
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@ -33,8 +33,7 @@ module csri #(parameter
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MIE = 12'h304,
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MIE = 12'h304,
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MIP = 12'h344,
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MIP = 12'h344,
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SIE = 12'h104,
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SIE = 12'h104,
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SIP = 12'h144
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SIP = 12'h144) (
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic InstrValidNotFlushedM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic CSRMWriteM, CSRSWriteM,
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@ -41,11 +41,7 @@ module csrs #(parameter
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SCAUSE = 12'h142,
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SCAUSE = 12'h142,
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STVAL = 12'h143,
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STVAL = 12'h143,
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SIP= 12'h144,
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SIP= 12'h144,
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SATP = 12'h180,
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SATP = 12'h180) (
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// Constants
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ZERO = {(`XLEN){1'b0}},
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SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9)
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic InstrValidNotFlushedM,
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input logic CSRSWriteM, STrapM,
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input logic CSRSWriteM, STrapM,
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@ -63,15 +59,17 @@ module csrs #(parameter
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output logic IllegalCSRSAccessM
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output logic IllegalCSRSAccessM
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);
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);
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// Constants
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localparam ZERO = {(`XLEN){1'b0}};
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localparam SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9);
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// Supervisor mode CSRs sometimes supported
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if (`S_SUPPORTED) begin:csrs
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logic WriteSTVECM;
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logic WriteSTVECM;
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logic WriteSSCRATCHM, WriteSEPCM;
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logic WriteSSCRATCHM, WriteSEPCM;
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logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
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logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
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// write enables
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assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
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assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
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assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
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assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
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assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
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assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
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@ -117,13 +115,4 @@ module csrs #(parameter
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end
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end
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endcase
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endcase
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end
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end
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end else begin
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assign WriteSSTATUSM = 0;
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assign CSRSReadValM = 0;
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assign SEPC_REGW = 0;
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assign STVEC_REGW = 0;
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assign SCOUNTEREN_REGW = 0;
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assign SATP_REGW = 0;
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assign IllegalCSRSAccessM = 1;
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end
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endmodule
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endmodule
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@ -45,8 +45,6 @@ module csru #(parameter
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output logic IllegalCSRUAccessM
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output logic IllegalCSRUAccessM
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);
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);
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// Floating Point CSRs in User Mode only needed if Floating Point is supported
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if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
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logic [4:0] FFLAGS_REGW;
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logic [4:0] FFLAGS_REGW;
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logic [2:0] NextFRMM;
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logic [2:0] NextFRMM;
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logic [4:0] NextFFLAGSM;
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logic [4:0] NextFFLAGSM;
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@ -82,9 +80,4 @@ module csru #(parameter
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endcase
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endcase
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end
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end
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end
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end
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end else begin // if not supported
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assign FRM_REGW = 0;
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assign CSRUReadValM = 0;
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assign IllegalCSRUAccessM = 1;
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end
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endmodule
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endmodule
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@ -41,18 +41,18 @@ module privdec (
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input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits
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input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits
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output logic IllegalInstrFaultM, // Illegal instruction
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output logic IllegalInstrFaultM, // Illegal instruction
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output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
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output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
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output logic sretM, mretM,
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output logic sretM, mretM, // return instructions
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output logic wfiM, sfencevmaM
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output logic wfiM, sfencevmaM // wfi / sfence.fma instructions
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);
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);
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logic IllegalPrivilegedInstrM;
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logic IllegalPrivilegedInstrM; // privileged instruction isn't a legal one or in legal mode
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logic WFITimeoutM;
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logic WFITimeoutM; // WFI reaches timeout threshold
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logic StallMQ;
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logic ebreakM, ecallM; // ebreak / ecall instructions
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logic ebreakM, ecallM;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Decode privileged instructions
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// Decode privileged instructions
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///////////////////////////////////////////
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///////////////////////////////////////////
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assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED &
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assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED &
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(PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR);
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(PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR);
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assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
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assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
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@ -65,6 +65,7 @@ module privdec (
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///////////////////////////////////////////
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///////////////////////////////////////////
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// WFI timeout Privileged Spec 3.1.6.5
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// WFI timeout Privileged Spec 3.1.6.5
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///////////////////////////////////////////
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///////////////////////////////////////////
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if (`U_SUPPORTED) begin:wfi
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if (`U_SUPPORTED) begin:wfi
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logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
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logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
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assign WFICountPlus1 = WFICount + 1;
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assign WFICountPlus1 = WFICount + 1;
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@ -75,24 +76,14 @@ module privdec (
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Extract exceptions by name and handle them
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// Extract exceptions by name and handle them
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///////////////////////////////////////////
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///////////////////////////////////////////
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assign BreakpointFaultM = ebreakM; // could have other causes from a debugger
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assign BreakpointFaultM = ebreakM; // could have other causes from a debugger
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assign EcallFaultM = ecallM;
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assign EcallFaultM = ecallM;
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///////////////////////////////////////////
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// sfence.vma causes TLB flushes
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///////////////////////////////////////////
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// sets ITLBFlush to pulse for one cycle of the sfence.vma instruction
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// In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program.
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// But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and
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// the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush
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// after a cycle AND pulse it for another cycle on any further back-to-back sfences.
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// flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ));
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// assign ITLBFlushF = sfencevmaM & ~StallMQ;
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// assign DTLBFlushM = sfencevmaM;
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///////////////////////////////////////////
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///////////////////////////////////////////
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// Fault on illegal instructions
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// Fault on illegal instructions
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///////////////////////////////////////////
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///////////////////////////////////////////
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assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
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assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
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assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM |
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assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM |
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WFITimeoutM;
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WFITimeoutM;
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@ -155,7 +155,7 @@ module testbench;
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`define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q
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`define MCOUNTEREN `CSR_BASE.csrm.mcounteren.MCOUNTERENreg.q
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`define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q
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`define SCOUNTEREN `CSR_BASE.csrs.csrs.SCOUNTERENreg.q
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`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
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`define MSCRATCH `CSR_BASE.csrm.MSCRATCHreg.q
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`define SSCRATCH `CSR_BASE.csrs.csrs.SSCRATCHreg.q
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`define SSCRATCH `CSR_BASE.csrs.csrs.csrs.SSCRATCHreg.q
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`define MTVEC `CSR_BASE.csrm.MTVECreg.q
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`define MTVEC `CSR_BASE.csrm.MTVECreg.q
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`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
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`define STVEC `CSR_BASE.csrs.csrs.STVECreg.q
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`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
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`define SATP `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
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@ -700,16 +700,16 @@ module testbench;
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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case(ExpectedCSRArrayW[NumCSRPostWIndex])
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"mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW)
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"mhartid": `checkCSR(`CSR_BASE.csrm.MHARTID_REGW)
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"mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW)
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"mstatus": `checkCSR(`CSR_BASE.csrm.MSTATUS_REGW)
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"sstatus": `checkCSR(`CSR_BASE.csrs.SSTATUS_REGW)
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"sstatus": `checkCSR(`CSR_BASE.csrs.csrs.SSTATUS_REGW)
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"mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW)
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"mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW)
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"mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW)
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"mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW)
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"mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW)
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"mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW)
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"medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
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"medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW)
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"mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
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"mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW)
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"mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
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"mtval": `checkCSR(`CSR_BASE.csrm.MTVAL_REGW)
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"sepc": `checkCSR(`CSR_BASE.csrs.SEPC_REGW)
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"sepc": `checkCSR(`CSR_BASE.csrs.csrs.SEPC_REGW)
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"scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
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"scause": `checkCSR(`CSR_BASE.csrs.csrs.SCAUSE_REGW)
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"stvec": `checkCSR(`CSR_BASE.csrs.STVEC_REGW)
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"stvec": `checkCSR(`CSR_BASE.csrs.csrs.STVEC_REGW)
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"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
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"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
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"mip": begin
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"mip": begin
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`checkCSR(`CSR_BASE.csrm.MIP_REGW)
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`checkCSR(`CSR_BASE.csrm.MIP_REGW)
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@ -738,7 +738,7 @@ module testbench;
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// New IP spoofing
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// New IP spoofing
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logic globalIntsBecomeEnabled;
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logic globalIntsBecomeEnabled;
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assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22));
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assign globalIntsBecomeEnabled = (`CSR_BASE.csrm.WriteMSTATUSM || `CSR_BASE.csrs.csrs.WriteSSTATUSM) && (|(`CSR_BASE.CSRWriteValM & (~`CSR_BASE.csrm.MSTATUS_REGW) & 32'h22));
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logic checkInterruptM;
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logic checkInterruptM;
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assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM;
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assign checkInterruptM = dut.core.ieu.InstrValidM & ~dut.core.priv.priv.trap.InstrPageFaultM & ~dut.core.priv.priv.trap.InterruptM;
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