From 53c8042276bcc2bb759d18eba007854c431d7b67 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 13 Jan 2023 15:56:10 -0600
Subject: [PATCH] Signal renames for ras.

---
 pipelined/src/ifu/RAsPredictor.sv | 23 +++++++++++++----------
 pipelined/src/ifu/bpred.sv        |  8 ++++----
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/RAsPredictor.sv
index 2fb98417f..3d82342fc 100644
--- a/pipelined/src/ifu/RAsPredictor.sv
+++ b/pipelined/src/ifu/RAsPredictor.sv
@@ -33,13 +33,16 @@ module RASPredictor
     )
   (input logic              clk,
    input logic              reset,
-   input logic              pop,
-   output logic [`XLEN-1:0] popPC,
-   input logic              push,
+   input logic              PopF,
+   output logic [`XLEN-1:0] RASPCF,
+   input logic              PushE,
    input logic              incr,
-   input logic [`XLEN-1:0]  pushPC
+   input logic [`XLEN-1:0]  PCLinkE
    );
 
+  // *** need to update so it either doesn't push until the memory stage
+  // or need to repair flushed push.
+  // *** need to repair popped and then flushed returns.
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
@@ -47,13 +50,13 @@ module RASPredictor
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
   
-  assign CounterEn = pop | push | incr;
+  assign CounterEn = PopF | PushE | incr;
 
-  assign PtrD = pop ? PtrM1 : PtrP1;
+  assign PtrD = PopF ? PtrM1 : PtrP1;
 
   assign PtrM1 = PtrQ - 1'b1;
   assign PtrP1 = PtrQ + 1'b1;
-  // may have to handle a push and an incr at the same time.
+  // may have to handle a PushE and an incr at the same time.
   // *** what happens if jal is executing and there is a return being flushed in Decode?
 
   flopenr #(Depth) PTR(.clk(clk),
@@ -67,12 +70,12 @@ module RASPredictor
     if(reset) begin
       for(index=0; index<StackSize; index++)
  memory[index] <= {`XLEN{1'b0}};
-    end else if(push) begin
-      memory[PtrP1] <= #1 pushPC;
+    end else if(PushE) begin
+      memory[PtrP1] <= #1 PCLinkE;
     end
   end
 
-  assign popPC = memory[PtrQ];
+  assign RASPCF = memory[PtrQ];
   
   
 endmodule
diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv
index 7784d813c..53bd4bafd 100644
--- a/pipelined/src/ifu/bpred.sv
+++ b/pipelined/src/ifu/bpred.sv
@@ -156,11 +156,11 @@ module bpred (
   // *** needs to include flushX
   RASPredictor RASPredictor(.clk(clk),
        .reset(reset),
-       .pop(PredInstrClassF[2] & ~StallF),
-       .popPC(RASPCF),
-       .push(InstrClassE[3] & ~StallE),
+       .PopF(PredInstrClassF[2] & ~StallF),
+       .RASPCF,
+       .PushE(InstrClassE[3] & ~StallE),
        .incr(1'b0),
-       .pushPC(PCLinkE));
+       .PCLinkE);
 
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF;