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Merge pull request #528 from davidharrishmc/dev

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Svnapot bug fix
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Rose Thompson 2023-12-13 21:30:47 -08:00 committed by GitHub
commit 53bf68a585
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7 changed files with 47 additions and 30 deletions
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6
sim/Makefile
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@ -15,6 +15,8 @@ all: riscoftests memfiles coveragetests
# Link Linux test vectors # Link Linux test vectors
#cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
wally-riscv-arch-test: wallyriscoftests memfiles
coverage: coverage:
#make -C ../tests/coverage --jobs #make -C ../tests/coverage --jobs
#iter-elf.bash --cover --search ../tests/coverage #iter-elf.bash --cover --search ../tests/coverage
@ -50,6 +52,10 @@ riscoftests:
# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
make -C ../tests/riscof/ make -C ../tests/riscof/
wallyriscoftests:
# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
make -C ../tests/riscof/ wally-riscv-arch-test
memfiles: memfiles:
make -f makefile-memfile wally-sim-files --jobs make -f makefile-memfile wally-sim-files --jobs

16
sim/imperas.ic
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@ -56,8 +56,8 @@
# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1 # Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
--override cpu/Svadu=T --override cpu/Svadu=T
--override cpu/updatePTEA=F #--override cpu/updatePTEA=F
--override cpu/updatePTED=F #--override cpu/updatePTED=F
# THIS NEEDS FIXING to 16 # THIS NEEDS FIXING to 16
@ -81,12 +81,12 @@
# #
--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL --callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL
--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM --callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 " # SDC --callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 " # CLINT --callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- " # PLIC --callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- " # UART0 error - 0x10000000 - 0x100000FF --callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF
--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- " # GPIO error - 0x10069000 - 0x100600FF --callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF
--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw--A- --4- " # SPI error - 0x10040000 - 0x10040FFF --callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF
--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM --callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
# Enable the Imperas instruction coverage # Enable the Imperas instruction coverage

4
src/mmu/tlb/tlb.sv
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@ -90,6 +90,7 @@ module tlb import cvw::*; #(parameter cvw_t P,
logic Misaligned; logic Misaligned;
logic MegapageMisaligned; logic MegapageMisaligned;
logic PTE_N; // NAPOT page table entry logic PTE_N; // NAPOT page table entry
logic NAPOT4; // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region
if(P.XLEN == 32) begin if(P.XLEN == 32) begin
assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0
@ -105,10 +106,11 @@ module tlb import cvw::*; #(parameter cvw_t P,
end end
assign VPN = VAdr[P.VPN_BITS+11:12]; assign VPN = VAdr[P.VPN_BITS+11:12];
assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4
tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush, .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOp, .DisableTranslation, .TLBFlush,
.PTEAccessBits, .CAMHit, .Misaligned, .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4,
.TLBMiss, .TLBHit, .TLBPageFault, .TLBMiss, .TLBHit, .TLBPageFault,
.UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType); .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);

3
src/mmu/tlb/tlbcontrol.sv
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@ -41,6 +41,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
input logic [11:0] PTEAccessBits, input logic [11:0] PTEAccessBits,
input logic CAMHit, input logic CAMHit,
input logic Misaligned, input logic Misaligned,
input logic NAPOT4, // pte.ppn[3:0] = 1000, indicating 64 KiB continuous NAPOT region
output logic TLBMiss, output logic TLBMiss,
output logic TLBHit, output logic TLBHit,
output logic TLBPageFault, output logic TLBPageFault,
@ -86,7 +87,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
// check if reserved, N, or PBMT bits are malformed w in RV64 // check if reserved, N, or PBMT bits are malformed w in RV64
assign BadPBMT = PTE_PBMT != 0 & (~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE) | assign BadPBMT = PTE_PBMT != 0 & (~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE) |
{PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs; {PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs;
assign BadNAPOT = PTE_N & ~P.SVNAPOT_SUPPORTED; // N must be be 0 if CVNAPOT is not supported assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region
assign BadReserved = PTE_RESERVED; // Reserved bits must be zero assign BadReserved = PTE_RESERVED; // Reserved bits must be zero
// Check whether the access is allowed, page faulting if not. // Check whether the access is allowed, page faulting if not.

2
testbench/testbench.sv
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@ -271,7 +271,7 @@ module testbench;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
if(TestBenchReset) test = 1; if(TestBenchReset) test = 1;
if (TEST == "coremark") if (TEST == "coremark")
if (dut.core.EcallFaultM) begin if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done."); $display("Benchmark: coremark is done.");
$stop; $stop;
end end

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.reference_output
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@ -108,6 +108,10 @@ beef0aa0 # Test 11.3.1.3.7(b): check successful read/write when D=0 and SVADU=1
00000000 00000000
BEEF0660 # Test 11.3.1.3.9: NAPOT read BEEF0660 # Test 11.3.1.3.9: NAPOT read
0550DEAD 0550DEAD
0000000d # Test 11.3.1.3.9: page fault on malformed NAPOT PTE
00000000
00000bad
00000000
0000000f # Test 11.3.1.3.10: PBMT; write page fault because menvcfg.PBMTE = 0 0000000f # Test 11.3.1.3.10: PBMT; write page fault because menvcfg.PBMTE = 0
00000000 00000000
00000009 # ecall from going to M mode from S mode 00000009 # ecall from going to M mode from S mode

38
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
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@ -86,22 +86,23 @@ test_cases:
.8byte 0x0000000080018040, 0x20000000200800DF, write64_test# Vaddr 0x8000, Paddr = 0x80200000, PBMT = 1 .8byte 0x0000000080018040, 0x20000000200800DF, write64_test# Vaddr 0x8000, Paddr = 0x80200000, PBMT = 1
.8byte 0x0000000080018048, 0x40000000200800DF, write64_test# Vaddr 0x9000, Paddr = 0x80200000, PMBT = 2 .8byte 0x0000000080018048, 0x40000000200800DF, write64_test# Vaddr 0x9000, Paddr = 0x80200000, PMBT = 2
.8byte 0x0000000080018050, 0x60000000200800DF, write64_test# Vaddr 0xA000, Paddr = 0x80200000, PMBT = 3 .8byte 0x0000000080018050, 0x60000000200800DF, write64_test# Vaddr 0xA000, Paddr = 0x80200000, PMBT = 3
.8byte 0x0000000080018080, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x0000000080018080, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x0000000080018088, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x0000000080018088, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x0000000080018090, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x0000000080018090, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x0000000080018098, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x0000000080018098, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180A0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180A0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180A8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180A8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180B0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180B0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180B8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180B8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180C0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180C0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180C8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180C8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180D0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180D0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180D8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180D8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180E0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180E0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180E8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180E8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180F0, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180F0, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x00000000800180F8, 0x80000000200800DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT .8byte 0x00000000800180F8, 0x80000000200820DF, write64_test# Vaddr 0x10000, Paddr = 0x80200000, NAPOT
.8byte 0x0000000080018150, 0x80000000200800DF, write64_test# Vaddr 0x20000, Paddr = 0x80200000, NAPOT malformed with ppn[3] =0
# Level 0 page table B # Level 0 page table B
.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage .8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
@ -208,7 +209,7 @@ test_cases:
# Now set ADUE bit # Now set ADUE bit
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output
.8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.ADUE = 1 .8byte 0x0, 0x2000000000000000, write_menvcfg # set menvcfg.HADE = 1
.8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output .8byte 0x0, 0x0, goto_s_mode # change to S mode, 0xb written to output
# Since SVADU is 1, there are no faults when A/D=0 # Since SVADU is 1, there are no faults when A/D=0
@ -226,6 +227,9 @@ test_cases:
# test 11.3.1.3.9 NAPOT read # test 11.3.1.3.9 NAPOT read
.8byte 0x1A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page .8byte 0x1A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page
# test 11.3.1.3.9 NAPOT read
.8byte 0x2A400, 0x0550DEADBEEF0660, read64_test # read from NAPOT 64 KiB page with malformed PTE should page fault
# test 11.3.1.3.10 PBMT checks # test 11.3.1.3.10 PBMT checks
.8byte 0x8040, 0x1212343456567878, write64_test # Write fault with PBMT when menvcfg.PBMTE = 0 .8byte 0x8040, 0x1212343456567878, write64_test # Write fault with PBMT when menvcfg.PBMTE = 0
.8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output .8byte 0x0, 0x0, goto_m_mode # change to M mode, 0x9 written to output