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Added tentative spi_send_byte function.

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This commit is contained in:
Jacob Pease 2024-07-19 12:30:32 -05:00
parent 34e89e842c
commit 53b2a51c89
2 changed files with 28 additions and 1 deletions
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27
fpga/zsbl/spi.c
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@ -5,6 +5,10 @@ void write_reg(uintptr_t addr, uint32_t value) {
*loc = value; *loc = value;
} }
void read_red(uintptr_t addr) {
return *(volatile uint32_t *) addr;
}
// Initialize Sifive FU540 based SPI Controller // Initialize Sifive FU540 based SPI Controller
void spi_init() { void spi_init() {
// Disable interrupts by default // Disable interrupts by default
@ -22,3 +26,26 @@ void spi_init() {
SIFIVE_SPI_DELAY1_INTERXFR(0)); SIFIVE_SPI_DELAY1_INTERXFR(0));
} }
// Sends and receives a single byte
uint8_t spi_send_byte(uint8_t byte) {
// Write byte to transfer fifo
write_reg(SPI_TXDATA, byte);
/* Not sure how necessary this is. Will keep commented for now.
// Wait a decent amount of time for data to send
for (int i = 0; i < 100; i++) {
__asm__ volatile("nop");
}
*/
// Wait for data to come into receive fifo
while (read_reg(SPI_IP) != 2) {}
// Read received data
result = read_reg(SPI_RXDATA);
// Return result
return result;
}

2
fpga/zsbl/spi.h
View File

@ -39,7 +39,7 @@
void write_reg(uintptr_t addr, uint32_t value); void write_reg(uintptr_t addr, uint32_t value);
uint32_t read_reg(uintptr_t addr); uint32_t read_reg(uintptr_t addr);
void spi_send_byte(uint8_t byte); uint8_t spi_send_byte(uint8_t byte);
void spi_init(); void spi_init();
#endif #endif