From 5cf686429d5d75cac901d202cd3dc7f8f0f59342 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 18 Jan 2022 17:29:21 -0600 Subject: [PATCH 1/2] Merged in the debug ila updates. --- fpga/constraints/debug2.xdc | 27 ++++++++++++++++++++++++++ pipelined/src/ieu/datapath.sv | 2 +- pipelined/src/ieu/regfile.sv | 2 +- pipelined/src/privileged/csr.sv | 2 +- pipelined/src/privileged/csrm.sv | 2 +- pipelined/src/privileged/csrs.sv | 2 +- pipelined/src/privileged/privileged.sv | 2 +- 7 files changed, 33 insertions(+), 6 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 3aeff5819..7281fa50b 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -591,3 +591,30 @@ create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe127] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127] +connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe128] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128] +connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/hart/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe129] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129] +connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/hart/ieu/dp/regf/rf[4]__0[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe130] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe130] +connect_debug_port u_ila_0/probe130 [get_nets [list wallypipelinedsoc/hart/ieu/dp/RegWriteW]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe131] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131] +connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/hart/priv.priv/CSRWriteM} ]] diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index c5987034d..0c1ff3e32 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -58,7 +58,7 @@ module datapath ( output logic [`XLEN-1:0] WriteDataM, // Writeback stage signals input logic StallW, FlushW, - input logic RegWriteW, +(* mark_debug = "true" *) input logic RegWriteW, input logic SquashSCW, input logic [2:0] ResultSrcW, output logic [`XLEN-1:0] ReadDataW, diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 9b1610968..e6407a894 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -39,7 +39,7 @@ module regfile ( localparam NUMREGS = `E_SUPPORTED ? 16 : 32; // only 16 registers in E mode - logic [`XLEN-1:0] rf[NUMREGS-1:1]; +(* mark_debug = "true" *) logic [`XLEN-1:0] rf[NUMREGS-1:1]; integer i; // three ported register file diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index d4110666b..ae37c0ccc 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -79,7 +79,7 @@ module csr #(parameter logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM, CSRReadValM; logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM; - logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; +(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 48f462df8..35fddbee7 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -89,7 +89,7 @@ module csrm #(parameter ); logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW; - logic [`XLEN-1:0] MSCRATCH_REGW; +(* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index d0e20ec4d..a4c1438d3 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -78,7 +78,7 @@ module csrs #(parameter logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; - logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; +(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW; (* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW; logic InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 8f58fd13a..d1753f292 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -31,7 +31,7 @@ module privileged ( input logic clk, reset, input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, - input logic CSRReadM, CSRWriteM, +(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, input logic [`XLEN-1:0] SrcAM, input logic [`XLEN-1:0] PCM, input logic [31:0] InstrM, From 305fccfe7a2c266db15c2fbe8964091eb297e657 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 18 Jan 2022 21:13:18 -0600 Subject: [PATCH 2/2] Fixed fpga ila debug to match lsu changes. --- fpga/constraints/debug2.xdc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 7281fa50b..041803167 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -86,7 +86,7 @@ connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore/sdc create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe17] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] -connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu.bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu.bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu.bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu.bus.dcache.dcache/cachefsm/CurrState[3]} ]] +connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe18] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] @@ -574,7 +574,7 @@ connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/ create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe123] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123] -connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/ifu/busfsm/BusCurrState[2]} ]] +connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/hart/ifu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/ifu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/ifu/bus.busfsm/BusCurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe124] @@ -585,7 +585,7 @@ connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/hart/ifu/S create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe125] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125] -connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/lsu/busfsm/BusCurrState[2]} ]] +connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/hart/lsu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/hart/lsu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/hart/lsu/bus.busfsm/BusCurrState[2]} ]] create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe126]